ee9b0fa199
The code currently unconditionally flushes or invalidates the entire cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector for APs and after loading SMM handlers. This commit modifies this behavior to only perform these cache operations if the CPU does *not* support self-snooping. Self-snooping CPUs can maintain cache coherency within the core/ complex more efficiently. CPU with self-snoop enabled does not necessarily need to perform wbinvd to ensure data written to the cache is reflected in main memory. Self-snooping CPUs employ a write-back caching policy, combined with a cache coherence protocol, to manage data writes and ensure consistency between cache and main memory. When the BSP writes the SIPI vector or SMM handlers to memory, other units within the same CPU that might be caching these regions should be aware of the updates through the self-snooping mechanism. A full cache flush or invalidate to ensure cache contains reaches to main memory might be unnecessary and could negatively impact performance. By conditionally performing these cache operations based on `self_snooping_supported()`, we can optimize the boot process for CPUs that have advanced cache coherency features while maintaining correct behavior on older or simpler CPUs. TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce boot time by ~19-25ms. Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87182 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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