coreboot/src/vendorcode
Fabian Kunkel 7e61e6c4d0 UPSTREAM: amd/agesa/f16kb: Allow SATA Gen3
YangtzeSataResetService implements the SataSetMaxGen2 double.
The value should be only set, if the condition is met.
For testing, add
FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE;
to your BiosCallOuts.c, which enables GEN3 for the SATA ports.
Patch is tested with bap/e20xx board, Lubuntu 16.04 Kernel 4.4.
$ dmesg | grep ahci #before patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
$ dmesg | grep ahci #after patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode

BUG=None
BRANCH=None
TEST=None

Change-Id: I17a493b876a4be3236736b2116b331e465b159af
Original-Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Original-Reviewed-on: https://review.coreboot.org/15728
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362842
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-23 13:05:11 -07:00
..
amd UPSTREAM: amd/agesa/f16kb: Allow SATA Gen3 2016-07-23 13:05:11 -07:00
google tpm2: implement locking firmware rollback counter 2016-07-07 22:14:26 -07:00
intel UPSTREAM: soc/intel/quark: Pass in the memory initialization parameters 2016-07-09 01:40:13 -07:00
siemens UPSTREAM: intel/i210: Change API for function mainboard_get_mac_address() 2016-07-07 01:09:39 -07:00
Makefile.inc vendorcode/siemens: Add hwilib for Siemens specific info struct 2016-04-28 08:15:47 +02:00