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UPSTREAM: amd/agesa/f16kb: Allow SATA Gen3

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YangtzeSataResetService implements the SataSetMaxGen2 double.
The value should be only set, if the condition is met.
For testing, add
FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE;
to your BiosCallOuts.c, which enables GEN3 for the SATA ports.
Patch is tested with bap/e20xx board, Lubuntu 16.04 Kernel 4.4.
$ dmesg | grep ahci #before patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
$ dmesg | grep ahci #after patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode

BUG=None
BRANCH=None
TEST=None

Change-Id: I17a493b876a4be3236736b2116b331e465b159af
Original-Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Original-Reviewed-on: https://review.coreboot.org/15728
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362842
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Fabian Kunkel 2016-07-18 17:39:28 +02:00 • committed by chrome-bot
commit 7e61e6c4d0
1 changed files with 0 additions and 1 deletions
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src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c
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@ -78,7 +78,6 @@ FchInitResetSataProgram (
if ( LocalCfgPtr->SataSetMaxGen2 ) {
FchSataMode |= 0x04;
}
FchSataMode |= 0x04;
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x0A0), AccessWidth8, (UINT32)~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), 0, StdHeader);
FchSataClkMode = LocalCfgPtr->SataClkMode;