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coreboot/src
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Duncan Laurie 0e6ad000e3 haswell: Update GT PM register value 
This was changed to 0x80000000 in SA BWG 1.5.0.

BUG=chrome-os-partner:16862
BRANCH=none
TEST=build and boot on wtm2

Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50852
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2013-05-10 14:05:52 -07:00
..
arch Rename hardwaremain() to main() 2013-05-10 11:55:20 -07:00
console console: Make use of CONFIG_USE_OPTION_TABLE 2013-04-01 20:54:48 +02:00
cpu Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
device device tree: track init times 2013-05-01 15:36:25 -07:00
drivers [2/2] tps65090: re-factor for coreboot 2013-04-30 18:24:39 -07:00
ec Fix Google ChromeEC driver 2013-05-01 10:55:09 -07:00
include Rename hardwaremain() to main() 2013-05-10 11:55:20 -07:00
lib Rename hardwaremain() to main() 2013-05-10 11:55:20 -07:00
mainboard Rename hardwaremain() to main() 2013-05-10 11:55:20 -07:00
northbridge haswell: Update GT PM register value 2013-05-10 14:05:52 -07:00
southbridge Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
superio Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
vendorcode Eliminate use of pointers in coreboot table 2013-04-22 11:57:06 -07:00
Kconfig Drop CONFIG_AP_CODE_IN_CAR 2013-05-10 11:55:19 -07:00