coreboot/src/cpu/p6
Ronald G. Minnich 3a8ce19f87 we need cache_enable and disable visible.
failed attempts to get the acer northbridge to size ram
CV:S ----------------------------------------------------------------------
2001-04-12 18:36:53 +00:00
..
Config Changes from Eric for Alpha and other support 2001-03-13 04:22:19 +00:00
earlymtrr.inc use the safer movzwl instead of movl 2000-12-05 02:07:37 +00:00
l2_cache.c we need cache_enable and disable visible. 2001-04-12 18:36:53 +00:00
microcode.c add cvs identification string 2000-12-01 01:43:51 +00:00
mtrr.c Final updates for my code cleanup and alpha code merge. 2001-03-23 22:56:05 +00:00