coreboot/src/soc/amd
Karthikeyan Ramasubramanian bef5c40582 soc/amd/cezanne: Enable secure counters
Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.

BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.

Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-03 15:28:47 +00:00
..
cezanne soc/amd/cezanne: Enable secure counters 2021-12-03 15:28:47 +00:00
common soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 2021-11-30 21:56:00 +00:00
picasso cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI 2021-11-29 09:45:14 +00:00
stoneyridge soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 2021-11-30 21:56:00 +00:00
Kconfig