coreboot/src/southbridge
Stefan Tauner 97c8089430 sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5
The specification updates for ICH 9 & 10 require to leave the
register in its default state by reserving all of its bits.
Writing to it does not seem to make a difference anyway since
reading it afterwards does not reflect the write (tested on ICH10).
Therefore we should omit the writes but document this fact in the
code because it is easy to miss from the datasheet alone.

Change-Id: Iec0d79f926a826a80b90907f7861d0cb2ca30a5b
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-16 16:31:00 +00:00
..
amd src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode 2018-07-10 09:53:22 +00:00
broadcom src: Get rid of unneeded whitespace 2018-06-14 09:32:34 +00:00
intel sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5 2018-08-16 16:31:00 +00:00
nvidia Remove AMD K8 cpu and northbridge support 2018-05-31 03:42:11 +00:00
ricoh/rl5c476 sb/ricoh/rl5c476: Get rid of device_t 2018-05-21 14:01:49 +00:00
ti sb/ti/pci{1x2x,i7420,xx12}: Get rid of device_t 2018-05-22 07:18:08 +00:00
via/common src: Get rid of unneeded whitespace 2018-06-14 09:32:34 +00:00