05aa75bd3d
This commit introduces new board ID definitions for PTL-P and GCS in the PTLRVP mainboard code. The changes involve updating the `romstage.c` and `memory.c` files to handle these new board IDs, ensuring that memory configuration is correctly initialized based on the detected board type. Change-Id: Ia354db27a0124dcde2825e7a05a59ef5d539c4ef Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> |
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| .. | ||
| acpi | ||
| arch | ||
| commonlib | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| sbom | ||
| security | ||
| soc | ||
| southbridge | ||
| superio | ||
| vendorcode | ||
| Kconfig | ||