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coreboot/arch/x86/via
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Corey Osgood fcf66e3605 Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware 
and seems to be working.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1164 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-04-14 15:41:33 +00:00
..
c7.c This patch fixes a few small problems and gets cn700 to read from an IDE 2008-12-23 23:44:39 +00:00
c7.dts Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~15min to get to a memtest 2008-12-17 21:17:01 +00:00
stage0.S Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware 2009-04-14 15:41:33 +00:00
stage1.c Add core2 stage1.c dependency 2008-11-14 05:05:24 +00:00