Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI
read and write transactions. Limiting transfer size in the wrapper
allows to provide the API user with unlimited transfer size
transactions.
The tranfer size limitation is added to the spi_slave structure, which
is set up by the controller driver. The value of zero in this field
means 'unlimited transfer size'. It will work with existion drivers,
as they all either keep structures in the bss segment, or initialize
them to all zeros.
This patch addresses the problem for reads only, as coreboot is not
expected to require to write long chunks into SPI devices.
BRANCH=none
BUG=chrome-os-partner:32441, chrome-os-partner:31438
TEST=set transfer size limit to artificially low value (4K) and
observed proper operation on both Pistachio and ipq8086: both
Storm and Urara booted through romstage and ramstage.
Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232239
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is being triggered because the base address is added, but
there is nothing that needs done with it in set_resources step
and the ERROR message is tripping suspend resume test scripts.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=boot on samus and check for ERROR strings,
successfully run suspend_stress_test without failures
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231603
(cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480)
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3
Reviewed-on: https://chromium-review.googlesource.com/231604
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is the unified FSP interface code from coreboot.org. To present
a consistent interface with the FSPs for all of the different CPUs,
and to cut down on code maintenance, all of the FSPs use this
interface.
Bug=None
Test=Builds and runs on Broadwell
Change-Id: Idcca5c42b06c47c67946c706e424e0349405ddf0
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/221182
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/229573
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The TPS65913 PMIC has an RTC built into it. This change adds
a driver for it which implements the new RTC API.
BUG=chrome-os-partner:33764
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log
verified across multiple boots.
Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/229414
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
When the driver is included in bootblock, malloc() is not available.
Come to think of it, it is perfectly fine to use a statically
allocated structure for the SPI device descriptor - coreboot is
unlikely to require concurrent support of multiple SPI devices of the
same kind.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=bootblock on the FPGA board recognizes the installed Winbond
device:
coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting...
SF: Detected W25Q16 with page size 1000, total 200000
Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228959
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a ramstage driver for the TPM and allows the interrupt
to be configured in devicetree.cb.
The interrupt vector is set like other PNP devices, and the
interrupt polarity is set with a register configuration variable.
These values are written into locality 0 TPM_INT_VECTOR and
TPM_INT_ENABLE and then all interrupts are disabled so they are
not used in firmware but can be enabled by the OS.
It also adds an ACPI device for the TPM which will configure the
reported interrupt based on what has been written into the TPM
during ramstage. The _STA method returns enabled if CONFIG_LPC_TPM
is enabled, and the _CRS method will only report an interrupt if one
has been set in the TPM itself.
The TPM memory address is added by the driver and declared in the
ACPI code. In order to access it in ACPI a Kconfig entry is added for
the default TPM TIS 1.2 base address. Note that IO address 0x2e is
required to be declared in ACPI for the kernel driver to probe correctly.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=manual testing on samus:
1) Add TPM device in devicetree.cb with configured interrupt and
ensure that it is functional in the OS.
2) Test with active high and active low, edge triggered and level
triggered setups.
3) Ensure that with no device added to devicetree.cb that the TPM
is still functional in polling mode.
Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This moves the LPC TPM driver to drivers/pc80/tpm so it can
be turned into a ramstage driver with a chip.h
It includes no other changes yet.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=emerge-samus coreboot
Change-Id: I60ddd1d2a3e72bcf169a0b44e0c7ebcb87f4617d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226660
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER
configuration option enabled, so the verstage is missing the relevant
files in some Makefiles. This patch fixes the problem.
BRANCH=none
BUG=none
TEST=with the rest of the patches applied cosmos target builds fine
with COMMON_CBFS_SPI_WRAPPER enabled
Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223751
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch started out as an attempt to run linker scripts through the
preprocessor. However, since that required some more infrastructure
changes, the build system is so intertwined, and there are so many other
small issues that turned up and are easier to fix (and get running, and
test thoroughly) in a single go, it turned out a little bigger. In order
of appearance, it:
- wraps direct linker invocations in a macro to avoid the widespread
ifeq($(CONFIG_COMPILER_LLVM_CLANG),y) duplication.
- introduces an $(generic-deps) (equivalent to $(<class>-deps)) variable
for targets that all files depend on
- makes the $(src-to-obj) function usable in multiple places as the
authoritative way to get an output file name (even if the respective
source file is also under build/), and makes it preserve extensions on
everything except %.c and %.S (e.g. %.ld and %.asl)
- replaces the old $(<class>-postprocess) with a single
$(postprocessors) variable. The old ramstage-postprocess was weird
because it contained unescaped $(eval ...)s, meaning it gets executed
as soon as the variable is first substituted (and the other
$(eval ...) in the toplevel Makefile does essentially nothing). The
new mechanism is just $(eval ...)ed directly after the recursive parse
with no further magic. Files can freely append their own (escaped)
content to it and access variables valid in the calling context (like
$(<class>-objs)) directly.
- enhances the existing $(<class>-<type>-ccopts) mechanism with
$(<class>-generic-ccopts) and $(generic-<type>-ccopts) to reduce
duplication.
- makes .ld a type that can be added like a normal class file, causing
it to be preprocessed with the correct #defines for the current class
(needed for a follow-up feature). Migrates all linker scripts to this
mechanism, which allows us to get rid of the weird $(ldoptions)
mechanism (Kconfigs are replaced by preprocessor and no longer need to
be defined as symbols).
- removes duplicate $(INCLUDES) from $(CFLAGS)
- repairs the crazy state of MIPS Makefiles, which seem to have been
copied together from X86 despite having absolutely nothing in common
with that architecture. They were using the same code to paste
assembly pieces and linker scripts together without really needing it
for anything, and even accidentally relied on a Kconfig default set
in the arch/x86 subdirectory (I wish I was kidding). Changed them to
work equivalent to the arm/arm64 Makefiles which are far closer
related (also being SRAM-based platforms).
- moves the x86-specifc $(OPTION_TABLES_H) into the x86 Makefile.inc and
fixes an rule that would've had an empty target if it wasn't defined
- removes the custom ldscript-gathering variables for x86 bootblock and
romstage. The Makefile simply combines all .ld files that have been
added to the respective class now.
- uses the normal class build system to replace some of the custom rules
for autogenerated bootblock/crt0 files on x86, and removes some
hardcoded flags by using the normal $(...-ccopts) variables.
- moves the handling of .asl files from the global Makefile.inc to x86.
Changed to reuse the generic template for the preprocessing and C
compilation steps.
- removed the extra <name>.o linking step before linking an rmodule for
modules that don't require special linker flags (most of them).
- removes the incorrect assumption that there was a global $(LDFLAGS)
from the SMM Makefile.inc (it was named $(LDFLAGFS in one place so it
couldn't have been all that important ;) ).
- allow -j flag for parallel builds to be properly passed through to
vboot child invocation by using special $(MAKE) variable.
BUG=None
TEST=Built for Falco, Nyan_Blaze, Stout, Rush_Ryu and Urara. Binary
diffed old and new coreboot.rom (and some manually uncompressed stages),
confirmed that images/stages are byte-for-byte identical except for some
embedded timestamps and commit hashes. (Addresses in Falco/Stout
ramstages shifting slightly due to different link order for ASL object
files within their directory. Some addresses in Urara ramstage .rodata
and some relocation entries in rmodules moved around due to linking them
in fewer steps.)
Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The GIC is ARM's "Generic Interrupt Controller". This
change essentially implements the rudimentary support
for a GICv2 implementation that routes all interrupts
to Group1. This should also work for GICv1 with security
extensions.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted kernel using the code.
Change-Id: I4c5b84bfe888ac33fa01c8d64a3dffe1b5ddc823
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217512
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
GD25LQ64C and GD25LB64C have the same ID and settings.
BUG=chrome-os-partner:25907
BRANCH=baytrail
TEST=Boot with GD25LQ64 and check MRC data save/restore works.
Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/193238
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Patch from Macronix.
BUG=None
TEST=Compiled + verified system boot
BRANCH=Rambi
Signed-off-by: Patrick Ha <patrick@samsung.com>
Change-Id: I932b7041f6409ed8a5e65580e9e983908ab2dd3d
Reviewed-on: https://chromium-review.googlesource.com/211068
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: patrick Ha <patrick@samsung.com>
Commit-Queue: patrick Ha <patrick@samsung.com>
Tested-by: patrick Ha <patrick@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/211411
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This code ports antirollback module and tpm library from platform/vboot_reference.
names are modified to conform to Coreboot's style.
The rollback_index module is split in a bottom half and top half. The top half
contains generic code which hides the underlying storage implementation
the bottom half implements the storage abstraction.
With this change, the bottom half is moved to coreboot, while the top half stays
in vboot_reference.
TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link.
BUG=none
Branch=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e
Reviewed-on: https://chromium-review.googlesource.com/206065
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Storm devices use more recent Spansion flash, add its description to
the table of supported devices.
BUG=chrome-os-partner:29871
TEST=the updated firmware boots all the way to depthcharge
Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205182
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This makes it so that we always log the generic "system boot" event.
If boot count support has not been implemented, fake it.
BUG=chrome-os-partner:28772
BRANCH=nyan
TEST=booted on Big, ran "mosys eventlog list" and saw
"System boot" event logged with boot count == 0
Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204525
Reviewed-by: Julius Werner <jwerner@chromium.org>
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: I69b0a330acbff97ebb8dc3ce3e37f7452433b5dc
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197882
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2bd9b4250fe44c33a15f8615de4034cfff4cf3b5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d
Reviewed-on: https://chromium-review.googlesource.com/198324
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
The Eon SPI25 code had a number of issues:
- fix page write calculation
- fix erase segment
- fix id check
- fix sector size
- make commands EN25 generic
This make the code similar to other SPI25 devices used in coreboot.
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: Id83d94b7ae5ea1610804a943c657d95a29dc6247
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197881
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 090a8e4352890c43209bd17acc41281a3af89f16)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Conflicts:
src/drivers/spi/eon.c
Change-Id: I7667eab28b850790d92a591c869788d51c26a56c
Reviewed-on: https://chromium-review.googlesource.com/198323
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
There is redundancy in terms of use of init_timer. We have a Kconfig option to
decide whether a board has init_timer as well as we use stub for init_timer in
places where we do not have any init_timer defined. Thus, removing the Kconfig
option. Henceforth, all boards that do not have init_timer functionality can
include include a stub_timer if required.
BUG=None
BRANCH=None
TEST=Compiled successfully for all mainboard/google/ boards as well as all the
other boards that were compiling fine before this change using abuild still
compile fine. No additional errors introduced because of this change
Change-Id: Iaffec9ce92107e55d65cc7c9f317feeeba700242
Reviewed-on: https://chromium-review.googlesource.com/195250
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Since the same driver is going to be used at all coreboot stages, it
can not use malloc() anymore. Replace it with static allocation of the
driver container structure.
The read interface is changed to spi_flash_cmd_read_slow(), because of
the problems with spi_flash_cmd_read_fast() implementation. In fact
there is no performance difference in the way the two interface
functions are implemented.
BUG=chrome-os-partner:27784
TEST=manual
. with all patches applied coreboot proceeds to attempting to load
the payload.
Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197931
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Coreboot has all necessary infrastructure to use the proper SPI flash
interface in bootblock for CBFS. This patch creates a common CBFS
wrapper which can be enabled on different platforms as required.
COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the
common CBFS interface and prevents default inclusion of all SPI chip
drivers, only explicitly configured ones will be included when the new
feature is enabled. Since the wrapper uses the same driver at all
stages, enabling the new feature will also make it necessary to
include the SPI chip drivers in bootblock and romstage images.
init_default_cbfs_media() can now be common for different platforms,
and as such is defined in the library.
BUG=none
TEST=manual
. with this change and the rest of the patches coreboot on AP148
comes up all the way to attempting to boot the payload (reading
earlier stages from the SPI flash along the way).
Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197800
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Use the RTC driver interface to find the timestamp for events instead of
reading the CMOS based RTC directly on x86 or punting on ARM. This makes
timestamps available on both architectures, assuming an RTC driver is
available.
BUG=None
TEST=Built and booted on nyan_big and link and verified that the timestamps
in the event log were accurate.
BRANCH=nyan
Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197798
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The AS3722 PMIC, like many PMICs, has an RTC built into it. This change adds a
driver for it which implements the new RTC API.
BUG=None
TEST=Built and booted with the event log code modified to use this interface.
Verified that events had accurate timestamps.
BRANCH=nyan
Change-Id: I400adccbf84221dcba8d520276bb91b389f72268
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197796
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This CL adds an API for RTC drivers, and implements its two functions, rtc_get
and rtc_set, for x86's RTC. The function which resets the clock when the CMOS
has lost state now uses the RTC driver instead of accessing the those registers
directly. The availability of "ALTCENTURY" is now set through a kconfig
variable so it can be available to the RTC driver without having to have a
specialized interface.
BUG=None
TEST=Built and booted on Link with the event log code modified to use the RTC
interface. Verified that the event times were accurate.
BRANCH=nyan
Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197795
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Most of the code related to the mc146818 is not related to the RTC and is
really for managing the CMOS storage. Since we intend to add a generic API
for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
This CL renames those functions so they start with cmos_ instead. There are
some places where rtc_init was called with a comment that says something about
starting the RTC. That wasn't correct before (the RTC is always running), but
it looks a little odd now that the function is called cmos_init.
This CL also opportunistically cleans up some style problems in this file.
BUG=None
TEST=Built for link. Built for nyan.
BRANCH=nyan
Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197794
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Add the device ID definitions and properties for the SPI chip used on
the AP148 board.
BUG=chrome-os-partner:27784
TEST=manual
. with the rest of the patches applied AP148 boots all the way to
trying to read the payload.
Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197895
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Some LPC initialiation can save some lines of code when being able
to use the functions `io_apic_read()` and `io_apic_write()`.
As these two functions are now public, remove them from the generic
driver as otherwise we get a build errors like the following.
[…]
Building roda/rk9; i386: ok, using i386-elf-gcc
Using payload /srv/jenkins/payloads/seabios/bios.bin.elf
Creating config file... (blobs, ccache) ok; Compiling image on 4 cpus in parallel .. FAILED after 12s!
Log excerpt:
coreboot-builds/roda_rk9/arch/x86/lib/ramstage.o: In function `io_apic_write':
/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/arch/x86/lib/ioapic.c:32: multiple definition of `io_apic_write'
coreboot-builds/roda_rk9/drivers/generic/ioapic/ramstage.o:/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/drivers/generic/ioapic/ioapic.c:22: first defined here
collect2: error: ld returned 1 exit status
make: *** [coreboot-builds/roda_rk9/generated/coreboot_ram.o] Error 1
make: *** Waiting for unfinished jobs....
[…]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3180
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
(cherry picked from commit ac75bc682b)
BUG=chrome-os-partner:28234
BRANCH=None
TEST=emerge-rambi coreboot
Change-Id: Ie829995e842c33ea82920799430c3e9f813be3da
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196262
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This consolidates all calls to spi_claim_bus() and spi_release_bus()
to a single location where spi_xfer() is called. This avoids confusing
(and potentially redundant) calls that were being done throughout the
generic spi_flash.c functions and chip-specific functions.
I don't think the current approach could even work since many chip
drivers assert /CS once and then issue multiple commands such as page
program followed by reading the status register. I suspect the reason
we didn't notice it on x86 is because the ICH/PCH handled each
individual command correctly (spi_claim_bus() and spi_release_bus()
are noops) in spite of the broken code.
BUG=none
BRANCH=none
TEST=tested on nyan and link
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I3257e2f6a2820834f4c9018069f90fcf2bab05f6
Reviewed-on: https://chromium-review.googlesource.com/194510
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This adds a wrapper function and a Kconfig variable to differentiate
between SPI controllers which use atomic cycle sequencing versus
those where the transaction sequence is controlled manually. Currently
this boils down to x86 vs. non-x86.
Yes, it's hideous. The current API only worked because, for better or
worse, x86 platforms have been homogeneous in this regard since they
started using SPI as an alternative to FWH for boot flash. Now that
we have non-x86 platforms which use general purpose SPI controllers,
we should overhaul the entire SPI infrastructure to be more adaptable.
BUG=none
BRANCH=none
TEST=tested on nyan and link
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: If8ccc9400a9d04772a195941a42bc82d5ecc1958
Reviewed-on: https://chromium-review.googlesource.com/195283
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This attempts to isolate/fix some x86-isms:
- Translate flash offset to memory-mapped address only on x86.
- Guard ACPI-dependent line of code
- Use a Kconfig variable for SPI bus when probing the flash rather
than assuming the bus is always on bus 0.
- Zero-out timestamp on non-x86 until we have a better abstraction.
(note: this is based off of some of Gabe's earlier work)
BUG=none
BRANCH=none
TEST=needs testing
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I887576d8bcabe374d8684aa5588f738b36170ef7
Reviewed-on: https://chromium-review.googlesource.com/191203
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
This severs a dependency the eventlog code has on initializing
chipset/SoC SPI controller. Currently elog_init() calls spi_init()
as a catch-all. This worked for x86 since the SPI controller is only
used for one thing on existing platforms. As we add eventlogging
support to non-x86 platforms we need to consider the more generalized
case where the assumptions about how SPI works on x86 are no longer
valid.
BUG=none
BRANCH=none
Signed-off-by: David Hendricks <dhendrix@chromium.org>
TEST=built and booted on Link, Beltino and Rambi. See below for
"mosys eventlog list" output on Link showing boot and suspend/resume
events (including lid close/open) added successfully.
localhost ~ # mosys eventlog list
0 | 2014-04-14 13:52:44 | Log area cleared | 4096
1 | 2014-04-14 13:52:44 | System boot | 50
2 | 2014-04-14 13:52:44 | EC Event | Power Button
3 | 2014-04-14 13:52:44 | SUS Power Fail
4 | 2014-04-14 13:52:44 | System Reset
5 | 2014-04-14 13:52:44 | ACPI Wake | S5
6 | 2014-04-14 13:53:25 | ACPI Enter | S3
7 | 2014-04-14 13:53:35 | ACPI Wake | S3
8 | 2014-04-14 13:53:35 | Wake Source | RTC Alarm | 0
9 | 2014-04-14 13:53:49 | ACPI Enter | S3
10 | 2014-04-14 13:54:00 | EC Event | Lid Open
11 | 2014-04-14 13:54:00 | ACPI Wake | S3
12 | 2014-04-14 13:54:00 | Wake Source | GPIO | 15
Change-Id: I26e25c0a856f7b8db5ab6b8e7e1acae291d2eadc
Reviewed-on: https://chromium-review.googlesource.com/194526
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Similar to the W25Q64DW, the W25Q32DW has basically the same
attributes as the earlier W25Q32 parts but with a different
value in the MSB of the ID.
BUG=none
BRANCH=none
TEST=tested on nyan, now SPI flash commands actually work.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I697768a443c98515d893f9cf8f8b4258ae0f159d
Reviewed-on: https://chromium-review.googlesource.com/191205
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
The old print simply said "Got idcode". This makes it actually
display what it got.
BUG=none
BRANCH=none
TEST=tested on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I8f1c8fde6e4ac00b12e74f925b7bcff83d1f69f3
Reviewed-on: https://chromium-review.googlesource.com/191204
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
This replaces a hard-coded bus number of 0 with a Kconfig variable,
CONFIG_BOOT_MEDIA_SPI_BUS. This removes an assumption made for x86
where this value is always 0 and makes it easy to add support for
other platforms where the bus number for the backing SPI flash is
more arbitrary.
BUG=none
BRANCH=none
TEST=tested on Nyan (bus=4) and Link (bus=0)
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I1e878a1628af7f4ccc2f39a70b2190192767e536
Reviewed-on: https://chromium-review.googlesource.com/194854
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
The new API is in use in depthcharge and is based around the "i2c_transfer"
function instead of i2c_read and i2c_write. The new function takes an array of
i2c_seg structures which represent each portion of the transfer after a start
bit and before the stop bit. If there's more than one segment, they're
seperated by repeated starts.
Some wrapper functions have also been added which make certain common
operations easy. These include reading or writing a byte from a register or
reading or writing a blob of raw data. The i2c device drivers generally use
these wrappers but can call the i2c_transfer function directly if the need
something different.
The tegra i2c driver was very similar to the one in depthcharge and was simple
to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and
replace the ones in coreboot. The Exynos 5420 driver was ported from the high
speed portion of the one in coreboot and was straightforward to port back. The
low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot
and were replaced with the depthcharge implementation.
BUG=None
TEST=Built and booted on nyan with and without EFS. Built and booted on, pit
and daisy.
BRANCH=None
Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/193561
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Depending on the platform the underlying regions vboot requires
may not be accessible through a memory-mapped interface. Allow
for non-memory-mapped regions by providing a region request
abstraction. There is then only a few touch points in the code to
provide compile-time decision making no how to obtain a region.
For the vblocks a temporary area is allocated from cbmem. They
are then read from the SPI into the temporarily buffer.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built and booted a rambi with vboot verification.
Change-Id: I828a7c36387a8eb573c5a0dd020fe9abad03d902
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190924
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Whenever spi_xfer is called and whenver it's implemented, the natural unit for
the amount of data being transfered is bytes. The API expected things to be
expressed in bits, however, which led to a lot of multiplying and dividing by
eight, and checkes to make sure things were multiples of eight. All of that
can now be removed.
BUG=None
TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
errors in the firmware log. Built for rambi.
BRANCH=None
Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192049
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The spi_flash_probe and and spi_setup_slave functions each took a max_hz
parameter and a spi_mode parameter which were never used.
BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None
Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192046
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Not doing so makes it fail when run at high frequency.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with EFS and with the TPM turned up to 400 KHz.
BRANCH=None
Change-Id: I1cfb69c55f03cb90f66f437289803d897a1aad5c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191812
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
As a first step towards removing hardcodes from the FUI support,
change the haswell call to i915_lightup to panel_lightup, and pass the
intel_dp * as a parameter. Get rid of the scalar arguments and make
them part of intel_dp. Get rid of file-scope variables and use the
ones in the intel_dp struct. In falco, use functions that peppy
uses. Drop slippy support for FUI, it's a dead board; if this is ok
I'll remove the files next.
And, incidentally, fix the broken RGBX constant and change it to BGRX.
BUG=None
TEST=build and boot on falco and peppy. Verify that the colors are now correct.
BRANCH=None
Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174932
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Add a Kconfig variable so that driver code knows whether
or not to use dual-output reads.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5
Reviewed-on: https://chromium-review.googlesource.com/177834
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Drop a lot of u-boot-isms and share common TIS API
between I2C driver and LPC driver.
BUG=none
TEST=Boot tested on pit
BRANCH=none
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e
Reviewed-on: https://chromium-review.googlesource.com/175670
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
We had brought this code in from the kernel but found it best to
use mainboard- or chipset specific versions. Firmware should
strive to be as non-generic as possible.
BUG=None
TEST=Builds and this code was not used anywhere
BRANCH=None
Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172625
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Move (and rename to make it clearer) the function that computes display
parameters from the dpcd and edid.
BUG=None
TEST=Build and boot on peppy. Doesn't break falco other builds.
BRANCH=None
Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171366
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Peppy had some issues with FUI. We decided it was time to create
peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
we generated a replay attack, then interpolated against the slippy
i915io.c to get something working.
Also, in preparation for moving code out of the mainboard gma.c to
generic driver code, we got rid of some hardcodes in the mainboard
gma.c that have no business being there. The worst were the
computation of gmch_[m,n] and it turns out that we had some
long-standing bugs related to confusion about 'bpp'. I've killed the
word bpp everywhere I could because there are at least 3 things that
correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
names are long because I want to avoid all the mistakes we've all been
making in the last year :-) Sadly, that means a lot of changes not just
peppy-related, but they are simple and in a good cause.
The test pattern generation is driven by a global variable in
mainboard/peppy/gma.c. I've found in the past that it's very useful
to have a function like this available, as one can activate it while
using a jtag debugger: halt at the right place in ramstage, set the
variable to 1, continue. It's not enough code to worry about always
including.
The last hard-codes for M and N registers are gone, and the function
to set from generic intel_dp.c code works. To avoid screen trash on a
dev mode boot, which we liked but nobody else did :-), we now take the
time to put a pleasing background color that sort of doubles as a
power LED.
Rough timing is ramstage start is at 2.2, and dev setup is done at
3.3. These new platforms are depressingly slow to boot. Rom init alone
is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
prompt. These CPUs are at least 10x faster and take much longer to get going.
Future work, once we get this through, is to move more functions to the
intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
That separation only existed because i915io.c was generated by a tool, and it
had lots of ugliness. Most ugliness is gone.
BUG=None
TEST=build and boot on peppy and get a screen, in both dev and normal modes.
BRANCH=None
Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/170013
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
The W25Q64DW spi part is programatically equivalent
to the other W25Q64 parts except it operates at 1.8V.
Just add a new entry with the appropriate ID.
BUG=chrome-os-partner:22292
BRANCH=None
TEST=SPI controller can program the part.
Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170011
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The locality is requested when the TPM is initialized and released when
it's cleaned up. There's no reason to set it to the same thing again and
restore it back to the same value before and after every transaction.
BUG=None
TEST=Built and booted on pit.
BRANCH=None
forward ported from https://chromium-review.googlesource.com/#/c/168400
Change-Id: I291d1f86f220ef0eff6809c6cb00459bf95aa5e0
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168584
Reviewed-by: Gabe Black <gabeblack@chromium.org>
I assume from the code in the TPM driver that the TPM spec defines
different types of delays and timeouts which each have a particular
duration, and that the TPM can tell you how long each type is if you ask
it. There was a large table, some members of a data structure, and a
function or two which managed the timeouts and figured their value for
different operations. The timeout values for the various "ordinals"
were never set in the vendor specific data structure, however, and
always defaulted to 2 minutes. Similarly the timeouts a, b, c, and d
were never overridden from their defaults. This change gets rid of all
the timeout management code and makes the "ordinal" timeout 2 minutes
and the a, b, c, and d timeouts 2 seconds, the larger of the two default
values.
This is a port from depthcharge to coreboot, original change:
https://chromium-review.googlesource.com/#/c/168363/
BUG=None
TEST=Built and booted on kirby
BRANCH=None
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I79696d6329184ca07f6a1be4f6ca85e1655a7aaf
Reviewed-on: https://chromium-review.googlesource.com/168583
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
