All X11 boards currently supported have Intel SPS without support for
S3/S5. Thus, drop it from Kconfig.
Note: not all X11 boards are server boards. When a X11 desktop or
workstation board should be added, this can be selected by the boards,
where S3/S5 work.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Correct unconnected pads that are configured different currently by
copying vendor configuration while porting the board.
Add internal pull resistors to all unconnected pads, that do not have an
external pull resistor, to prevent floating.
The pads have been determined by dissecting a dead board. This commit
only changes pads, that are not connected at all and don't have any via,
so we can be absolutely sure there is no other connection.
Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
(Re)configure various pads found by dissecting a dead board and vendor
firmware, as well as the BMC firmware:
- GPP_B14: input connected to jumper JBR1 - could be used to implement
"BIOS Recovery" ("Top-Block Swap") functionality; external pull-up
- GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify
the BMC about a thermal throttling event. Not implemented in vendor
firmware.
- GPP_C23: input connected to the CPU's CATERR# output; external pull-up
Not actively used by vendor firmware.
- GPP_D1: output connected to on-board and front panel power LEDs
- GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be
used for testing/debugging only, since it resets both slots at once.
Not actively used by vendor firmware.
- GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be
used for testing/debugging only, since it resets both slots at once.
Not actively used by vendor firmware.
- GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will
be used later in CB:48096 and CB:48097; external pull-up
- GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not
useful, since the IGD is not connected to any ports on this board.
External pulls ensure correct function of a dGPU even without driving
the gpios. Not used by vendor firmware.
- GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls
- GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not
used by vendor firmware.
Also add comments for documentation. While at it, mark ME-owned pads as
reserved.
Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
This change reorganizes FMAP for volteer to make use of the lower
16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to
RW_LEGACY. This is now possible because TGL supports memory mapping of
BIOS region greater than 16MiB.
Following changes are made in chromeos.fmd as part of this:
1. Move RW_SECTION_A and RW_MISC to lower 16MiB.
2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as
a placeholder in the lower half of the SPI flash.
3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a
larger region for ELOG.
4. Increase WP_RO to 8MiB to allow larger space for firmware
screens. GBB size is thus increased to 448KiB.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
AP_PEN_DET_ODL isolated by a diode and need to pull up internally.
BUG=b:160752604
BRANCH=dedede
TEST=Build and confirm waveform by google EE parter.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the PMC MUX and CONx devices for adlrvp for
conn2.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change restricts RW_DIAG region to lower 16MiB to ensure that the
extended BIOS checker for FMAP does not complain about 16MiB boundary
crossing.
I haven't updated any other regions to occupy the newly freed space
but it is fine since this board is dead and should be dropped from
coreboot soon.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change restricts SI_ME region to live below the 16MiB boundary to
ensure that no regions cross the 16MiB boundary as the extended BIOS
window checker for FMAP complains about it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds the PMC MUX and CONx devices for lindar. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=b:172533907
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
SATA_AHCI is already the default mode for CNL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Align the SATA mode names with soc/skl providing a consistent API.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The PCI devices P2SB and PMC are hidden by the FSP and cannot be
unhidden, because the FSP locks their configuration. Thus, setting them
to `on` is not correct. Therefore, set their state to hidden.
Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SATA_AHCI is already the default mode for SKL/KBL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: Ib5222c1b0314365b634f8585e8a97e0054127fe9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48378
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Skylake FSP isn't used by coreboot anymore. Therefore, drop the
misleading comment and the "KBLFSP" extension from the names of these
enums.
Also, drop the "MODE" extension to make their names shorter in general,
since it doesn't add any more value.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use proper indents in the devicetree and align `end` keywords.
Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI devices P2SB and PMC are hidden by the FSP. So instead turning
them off, set their state to hidden being able to allocate ressources
for them.
Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48371
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update lindar gpio settings for Synaptics trackpad no function issue.
Update I2C5 bus freq to 400kHz.
Improve Goodix Touchscreen power on sequence.
BUG=b:160013582
BRANCH=firmware-volteer-13521.B
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device. Verify trackpad function workable.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Unique among the Volteer devices, the volteer2_ti50 variant connects to
the TPM via I2C. This CL introduces the proper devicestree declarations
for the Linux kernel to recognize that.
overridetree.cb is shared between "sub"-variants volteer2 and
volteer2_ti50, so both will have two TPM nodes, the I2C being disabled
by default. The odd _ti50 variant then has code in variant.c to enable
the I2C node and disable the SPI node.
BUG=b:173461736
TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x
Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48223
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Power Limit2 (PL2) minimum value to the same as maximum value for
volteer variants like baseboard, delbin, eldrid, terrador and todor.
All other variants uses the DTT entries from baseboard devicetree since
there is no override present for those variants. DTT does not throttle PL2,
so this minimum value change here does not impact any existing behavior on
the system.
BUG=None
BRANCH=volteer
TEST=Build and test on volteer system
Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
refer to cb:45878
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
BUG=b:174735512
BRANCH=volteer
TEST=build and type-c display work
Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48268
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is
selected by their SoC soc/intel/cannonlake.
Change-Id: I9597746a217575b42f6325998b948e16b452231a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ib4e7ec948ca4d019ad82ebc5abe39fc408281cf4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48299
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add variant_configure_early_gpios() configuring early GPIOs to make the
difference clear.
Change-Id: I6e7c8c32963c9eeab4399947dac511442987cb45
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48298
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ibcb6322067285984bad70761fce34cfcb6ed8e0f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48297
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: I1ae9b54ed683000f65323b11747ce3280a1c7f2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48296
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow to specify which signature is to be checked.
Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Create the storo variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174284884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_STORO
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5ad41e0b2bc95b44733a2ad3c543267f3f56f9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Without the EC blob being present in the SPI flash, the board won't even
power up.
Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is an adapted copy of mainboard/example/min86 that is currently
only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't
expected to reach boot block at the moment. It will be extended in
future follow-up commits.
Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
DPTF paramerters form thermal team.
Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.
BUG=b:174514010
BRANCH=puff
TEST=build image and verified by thermal team.
Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than
APU_DP_BLON.
BUG=b:171954512
BRANCH=zork
TEST=validate the panel sequence with scope.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Create the copano variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174413884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COPANO
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released.
To ensure this, set the power enable signal in the bootblock GPIO table.
BUG=b:173676531
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.
Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use a new driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.
BUG=b:172397658
BRANCH=zork
TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:162192346
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Initiate device tree based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add implementation of EC smihandler
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
