Compiling efs_fmap_check.c depends on fmap_config.h already being
generated, so add this dependency.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Also add the Makefile dependency on the fmap_config.h file to make sure
that this file already exists when it's included.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP. An example of
implementation within Linux kernel is available [1].
There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated
driver on OS side can bind to it and handle this special setup. Since
PSP takes care of I2C controller power management, we need to remove
PowerResource object from DSDT.
BUG=b:204508404
BRANCH=guybrush
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The and-mask passed to the gpio_update32 call needs all 32 bits to be
set to ones. When building as 32 bit binary the -1UL will result in the
needed bit mask, but for a 64 bit build the constant would have 64 bits
set to ones which then gets truncated to 32 bits causing a compiler
error. Use 0xffffffff as bit mask instead which behaves correctly in
both cases and also clarifies what this is doing.
TEST=Timeless build for Chausie results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes a build failure when trying to build the code in 64 bit mode.
TEST=Timeless build for Chausie results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is required. Also add Kconfig option to enable sending message.
BUG=b:180701885
TEST=On a platform that supports SPL fusing. Build an image with an SPL
table indicating fusing is required, confirm that PSP indicates fusing
required and coreboot sends the appropriate command. A message indicating
PSP requested fusing will appear in the log: "PSP: Fuse SPL requested"
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
The gen2 ACP register definitions and locations are different from
previous models. Specific code is refactored into acp_gen1 and acp_gen2.
Update ACP register locations and definitions for gen2.
Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC
talk to each other via the system bus, there is no longer the
requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that
start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2
as the IOAPIC ID while most of their CPUs have more than 2 logical cores
resulting in the IOAPIC having the same ID as one of the LAPICs.
All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and
GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT
and IVRS ACPI tables and there's no MPTable support for those SoCs that
might also rely on those IDs being consistent.
This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID
from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes
sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a
CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4
bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of
IOAPIC IDs, this is non-standard.
TEST=AMD Mandolin and Google Liara still work.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Refactor existing acp code into acp_gen1 variant as preparation for gen2
variant in sabrina.
Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Check if FSP binary and coreboot FSP structures (fspmupd.h) match
sufficiently.
A change in minor number denotes less critical changes or additions
to the FSP API that still allow for the boot process to proceed.
A change of the AMD image revision major number will halt boot.
The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD
Picasso, Cezanne and Sabrina APUs.
BUG=b:184650244
TEST=build, boot and check fsp image revision info. Example:
FSP major = 1
FSP minor = 0
FSP revision = 5
FSP build = 0
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Introduce and use functions to translate eSPI IO/MMIO decode range IDs
into the corresponding register bits and the IO/MMIO range and size
register IDs into register offsets. This is a preparation to support the
additional eSPI decode ranges on Sabrina where not all enable bits and
base/size registers for one type of decode ranges are consecutive.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This aligns the register names more with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section. The EFS FMAP
partition is checked to ensure it begins at the expected location.
Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This will allow PSP verstage to write logs to the serial console. We
are no longer dependent on using a serial enabled PSP boot loader.
Ideally we would delete this psp printk and use the standard printk.
Since picasso doesn't currently support mapping the UART though, I'll
keep it for now.
BUG=b:215599230
TEST=Boot guybrush and verify PSP logs are output on serial console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibd77cc754fae5baccebe7adc5ae0790c79236d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
This comment was added with the AMD family 15h Trinity IOMMU support in
commit 88ebbeb7e2 and looks like a copy of
the comment about the subtractive decode ranges in the LPC device. The
IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this
is also not what the code does. This resource is the MMIO region to
configure the IOMMU instead, so fix the comment in all copies of the
IOMMU support code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The PM2 ACPIMMIO region should only be accessed with 8 bit accesses.
Using 16 or 32 bit read accesses will return the data from the first
byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in
only the first byte being written which is both unexpected behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge
and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on
Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is
only defined for Sabrina. Since the default value of undefined bits is 0
it isn't a problem to have descriptions for reserved reset status bits
on some SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V
and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the
existing I2C pad control registers the bit definitions are different, so
add a separate function to configure those pads which however still has
the same function signature and is compatible with same data structs
used for the devicetree settings. PPR #57243 Rev 1.50 was used as a
reference.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add platform_report_mode function which report current developer mode
status to the PSP. L1 widevine app in the PSP will use this information
to select key box.
BUG=b:211058864
TEST=build and boot guybrush
TEST=build picasso chrome os boards
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
This code is common to at least all Zen-based APUs (Picasso, Cezanne,
Sabrina) and is also useful outside of the SoC-specific dynamic ACPI
table generation code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-by: Eric Peers <epeers@google.com>
The VERSTAGE region is only needed when running verstage in the x86.
This change reduces the early ram size by 512 KiB when using PSP
verstage.
BUG=none
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I45ce421397807dbb1eb48aedd05209b91e89aa4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later
use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and
spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for
The AMD Sabrina SoC which is family 17h models A0h-AFh.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change splits the size of the console transfer region and size of
the bootblock/romstage Pre-RAM console region. This allows having a
larger Pre-RAM console while not impacting the size of the PSP verstage
console.
Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in
`setup_cbmem_console`, I chose to use the offsets provided in the
transfer buffer. It would be nice to eventually do this for all the
fields in the transfer buffer.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are no longer truncated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This implementation is the same for all SoC that select
SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR
CPU support code folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will verify that signed verstage binaries and the bootblock code
executing agree on the transfer buffer struct size.
BUG=b:213828947
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I597e38fe0a37416ffd3bc01fd974fa8f6610a88c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The existing common AMD SoC code supports some of AMD Family 17h Model
A0h SoC's PCI devices that however have different PCI IDs. Add the new
PCI ID defines to the PCI ID lists of the common PCI drivers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I50960e502c63a2ffcfed35178c5e7c9729ef061e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Define the register offsets and bits in a separate header file instead
of in the middle of the .c file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In espi_wait_channel_ready the return value of espi_get_configuration
didn't get checked before. In the case of the espi_send_command call in
espi_get_configuration returning CB_ERR, espi_get_configuration didn't
write to the local config variable, so if this happens in the first pass
of the do-while loop, the following espi_slave_is_channel_ready call
would use the uninitialized local config variable as parameter. Fix this
by checking the return value of espi_get_configuration.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use enum cb_err as return type of all remaining functions that only
return success or failure.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Use enum cb_err as return type of all functions that aren't exposed
outside of this compilation unit. The checks if a function has returned
a failure are replaced with checks if the return value isn't CB_SUCCESS
which is equivalent if only those two values are used, but also detects
a failure if any unexpected value would be returned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The intermediate ret variable isn't needed. espi_open_generic_io_window
only returns 0 or -1, so if ret is != 0, it has to be -1. This is a
preparation to use the enum cb_err type for the return values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03
define bit 9 of the PM_RST_STATUS register as internal Thermal Trip
reset status bit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the
first generation of PSP mailbox interface and not on the second
generation. The second generation of the PSP mailbox interface was
introduced with the AMD family 17h SoCs on which the DRAM is already
initialized before the x86 cores are released from reset.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Replace FCH_SC with FCH SPI in the printk messages to make those a bit
clearer and also remove an unneeded line break in another printk call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
