Recent changes to the ITE 8772F SIO code caused the initial fan PWM
to change from 0 to 50%; set it to 30% to reduce fan noise while
still providing some temp control before the OS/ACPI takes over.
TEST=build/boot stumpy to payload, verify fan noise is negligible.
Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81514
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Recent changes to the ITE 8772F SIO code caused the initial fan PWM
to change from 0 to 50%; set it to 30% to reduce fan noise while
still providing some temp control before the OS/ACPI takes over.
TEST=build/boot google/beltino to payload, verify fan noise is
negligible.
Change-Id: I0177235d73e051f02b5333cf1d735556382b919f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81513
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.
The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.
Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Haswell ThinkPads have Nvidia Optimus wired in on some models.
With recent coreboot changes, legacy VGA decode is now disabled
on the iGPU, and the iGPU itself is disabled, when a dGPU is
present. This is a problem on Optimus laptops, because it means
that the Intel GPU would be effectively disabled, when it is the
one that has to handle the framebuffer.
On these boards, you can enable ONBOARD_VGA_IS_PRIMARY so that
coreboot does not disable the iGPU. This is because on Optimus
laptops, the Nvidia GPU is only used for offloaded rendering.
Enable ONBOARD_VGA_IS_PRIMARY by default on these boards.
Change-Id: I8f1e0ca2861d1cc9a9ad41e7c9257aeca1a62a31
Signed-off-by: Leah Rowe <info@minifree.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81645
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also
initializing it (if ISH is enabled) to be NF2 (ISH_GP4). Also took
the liberty of alphabetizing all the ISH GPIOs to they're easier to
search through.
BUG=b:316421831
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
Make sure that brox device still boots up with this change.
Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81789
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously incorrect sets of SATA ports were enabled.
There are no publically available schematics, but I am almost certain
the new values are correct.
The original 0x33 value was carlessly copy pasted, and only enables
ports 0, 1, 4, 5, leaving 2, 3 disabled.
On the SFF, with 0x33 only the first 2 ports worked. I have verified
by plugging in devices under the stock firmware that 0, 1, 2 are the
ones that should be enabled, so setting the value to 0x7 per datasheet.
This was also tested in practice to work.
I don't have an MT, but I was told the two white ports didn't work
with 0x33, so those are most certainly ports 3, 4, hence me setting
the value to 0xf. If the MT's working ports are port 0, 1 on the PCH
this is correct.
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
<string.h> is supposed to provide <stdarg.h> and <stdio.h>
Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81853
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill GPIO table for Sundance.
BUG=b:327520553
TEST=emerge-nissa coreboot
Change-Id: I53ed5874347006985ca5231d1531fa519088f796
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81613
Tested-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
In next phase, craaskov will remove external fivr. Use the board
version to config external fivr for backward compatibility and
show message.
BUG=b:330253778
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:333605309
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared.
Change-Id: I6e2230715d783ea7108d71699fd19684ce19e2ff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds a new baseboard trulo. This commit is a stub which
only adds the minimum code needed for a successful build.
BUG=b:333314089
TEST=abuild -a -x -p none -t google/brya
Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and
POSTCAR_STAGE which are used by all Xeon-SP platforms.
After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0
is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X,
POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE.
TEST=Build and boot on intel/archercity CRB
Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set orientation of KD_KD101NE3_40TI to LB_FB_ORIENTATION_RIGHT_UP to
align the volume up/down direction with menu up/down in FW screen.
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage, and check FW screen on
wugtrio, test volume key behaves as expected.
BRANCH=corsola
Change-Id: Ie101cc8b983d3d16587f88fa787ed622e59d27eb
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81752
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch renames the 16MB FMD file to remove the baseboard-specific
name 'Nissa'. This allows other supported baseboards to utilize the
16MB SPI flash. Additionally, the patch attempts to create a generic,
unified 32MB FMD file for both brya and nissa variants.
BUG=b:333314089
TEST=Build and boot Nivviks.
Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81676
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The header file console/console.h is unused, just drop it.
TEST=abuild -t google/corsola -b wugtrio -a
TEST=abuild -t google/geralt -b ciri -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81685
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Correct verbtable value for pin widget 20 of Realtek ALC256 based on the
updated verbtable received from Realtek. Updated Version : 5.0.3.1. This
fixes the headset detection failure, when power_save is enabled in
legacy hda driver.
BUG=b:330433089
BRANCH=None
TEST=Verified headset on Brox
When connected to audiojack in power_save state of legacy hda driver,
headset is detected and audio is resumed.
Change-Id: I71b7d59b3ab5310a0b6cdb31fb5033f94263d151
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81654
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Terry Cheong <htcheong@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
BUG=b:332488817
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared
Change-Id: I6d7b35dbf8ac9b0abb42f64a947b4bb94f3c6b0f
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Daniel Kang <daniel.h.kang@intel.com>
Based on schematic and gpio table of sundance, generate overridetree.cb
settings for sundance.
BUG=b:328505938
TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage
Change-Id: I857be7bc7f98281cac57fef85bf9f3cef2ec14e9
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities such as system power down.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:328729536
BRANCH=brya
TEST=built and verified MSR PL2/PL4 values.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
[When connected 60W adapter without battery]
Before:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
After:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:60000000
[When connected 45W adapter without battery]
Before:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
After:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:45000000
constraint_2_power_limit_uw:45000000
Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81614
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In order to avoid the noise caused by the codec output to the audio
jack during the shutdown and poweron process, we will use GPP_A11 for
the codec power supply gate, keep low during the startup process, and
wait for the driver to turn on. This change does not affect the beep
output of depthcharge.
BUG=None
TEST=There is no squeaking sound when turning on and off
Change-Id: I5982be5a8d965086b46861f4c2c758d9bdee6e75
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81629
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This fixes a warning about casting an integer to a pointer, where the
integer has a different size than the pointer (UINT32).
Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81559
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make get_soc_power_limit_config() a public function to use on brya
variants. Add prefix 'variant_' for it.
BUG=None
BRANCH=brya
TEST=emerge-brya coreboot
Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81616
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add sundance supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE
BUG=b:332201349
TEST=Use part_id_gen to generate related settings
Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81612
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Deku has two Ethernet ports. Currently both get assigned the wrong
MAC address due to the LAN devices indices being swapped and
vpd ethernet_mac0() affects device eth1 and vpd ethernet_mac1() affects
device eth0.
Correct the device indices for LAN devices so ethernet_mac[0-1] in vpd
can apply to the correct ethernet ports.
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=vpd -s ethernet_mac0=<mac address0>
vpd -s ethernet_mac1=<mac address1>
reboot the system and check ifconfig
eth0 and eth1 MAC addresses are fetched correctly
Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81564
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the
code to get the proper pointer of the data for current CPU SKU.
I tried to override the PL4 value to 80W from 114W with following
table in ramstage.c as a test for bug b/328729536.
```
const struct cpu_power_limits limits[] = {
{PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000},
}
```
And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool.
- Before this patch: msr_pl4 was not changed, it's always 114
- After this patch: msr_pl4 was changed to 80
BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.
Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
ISH Firmware name needs to be configured only when full sensing
capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA
property needs to be added only when UFS is enabled through STORAGE_UFS
FW_CONFIG. Hence configure the ISH device at run-time based on
FW_CONFIG.
BUG=b:319164720
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:328505938
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_SUNDANCE
Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81347
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.
The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
not overlap.
- Works with non memory mapped flash (however all coreboot targets
currently do support this)
- If later stages can use their own page tables which fits better with
the vboot RO/RW flow
A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.
Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.
TEST: Booted to payload on google/vilbox and qemu/q35
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
