Commit graph

8 commits

Author SHA1 Message Date
Eric W. Biederman
2beb0a1bcc - Updates for the supermicro p4dc6 motherboard
- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
  with addresses that are not cached so writing to ram does not work.
  Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
  have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
  the 16bit entry code in SMP.
- A small number of fixes for warnings
2001-11-27 19:29:59 +00:00
Eric W. Biederman
d96aab9e06 - Delayed commit of code for the ASUS A7M motherboard
- VIA 686 cleanups from the A7M code (it now works in a different pci slot).
- Update of assembly printing routines to use the debug levels:
  TTYS0_TX_CHAR now becomes CONSOLE_<LEVEL>_TX_CHAR.
  It's more verbose but now the controls are the same as with the C code.
- Break off of loglevel.h from printk.h.  loglevel.h is safe for both
  the assembly routines and the C code to include.
- Next round of commits for the supermicro p4dc6
- SMP setup updates (Rons board is broken)
  I now allow the other SMP processors to report their existence.
  I really need to add a minimum time to run but that hasn't happened yet.
- SMP per motherboard table of apicids, as the assumption that they
  would always be 0 & 1 with only two cpus fails.
- RDRAM setup updates.  The code isn't done but it now works on more
  than one board at a time.
- More cacheram work.  Minor bug fixes and some macros to use it from C.
- Entry point changes so we no longer have to jump over our gdt.
- Added/Audited the cpufixup for the i786
- IDE intialization for the 82801 ich2 chip.
2001-11-13 03:43:37 +00:00
Eric W. Biederman
71be41d193 make.base(i386 & alpha)
make.base -- renamed OBJECTS to OBJECTS-1 to allow conditional compilation of objects
ldscript.base -- realized that assignemnts to the location counter inside of sections
           are relative to their start so simplfied the code
pirq_routing.h -- includeded types.h so we don't have suprises
hardwaremain.c -- unconditionally included arch/smp/mpsec.h
arch/i386/smp/Config introduced conitional on the compilation objects into
                  the compilation process
         ioapic.c -- removed (now) unneeded ifdef around this file
         mpsec.c -- removed (now) unneeded ifdef around this file

cpu/cpufixup.h -- Fix typo in the case when no cpufixup is needed.
parts/framebuffer.h -- Added a missing semicolon.
smp/atomic.h -- renamed second atmoic_inc to atomic_dec oops.

tyan/guinnes/Config -- reordered the options so they are grouped a little
                better and said mptable.o is dependent on HAVE_MP_TABLE
tyan/guiness/mainboard.c -- small change for clarity.

northsouthbridge/sis/630/northbridge.c
northsouthbridge/sis/630/southbridge.c
           -- Remove unused include of the now dead param.h

NLBConfig.py
          -- Only include numeric options in the linker script
          -- Update to handle adding a condition for when to build
             objects
2001-08-15 21:30:08 +00:00
Eric W. Biederman
ed8c9d7e0d Code changes from my work and the AMD760MP chipset.
The primary changes is the way in which printk works.
But there are many other assorted code cleanups.
Just look and see :)
2001-08-08 02:45:10 +00:00
Eric W. Biederman
228148aa23 Start of merge from work on the AMD760MP platform.
This is the safe part just additions to files, and comment changes
2001-08-07 19:46:37 +00:00
Li-Ta Lo
79ff9ed5cc MSR names for L2 cache init 2000-12-06 10:58:20 +00:00
Ronald G. Minnich
787deb4ae4 Fixes so we don't use any of the standard include paths 2000-10-17 22:58:51 +00:00
Ronald G. Minnich
69e023b385 Code reorg 2000-10-16 23:47:28 +00:00