1. Replace all pcidev_path_on_root() and is_dev_enabled()
functions combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
TEST=Able to build and boot without any regression seen on MTL.
Port of 'commit 50134eccbd ("soc/intel/alderlake: Make use
of is_devfn_enabled() function")'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch moves API "smbios_cpu_get_max_speed_mhz()"
to common code from board specific. This API was made
generic in 'commit d34364bdea ("soc/intel/alderlake:
Utilize `CPU_BCLK_MHZ` over dedicated macro")'
BUG=NONE
TEST=Boot and verified that SMBIOS max speed value is
correct on brya and rex.
(brya) dmidecode -t : "Max Speed: 4400 MHz"
(rex) dmidecode -t : "Max Speed: 3400 MHz"
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I87040ab23319097287e191d7fc9579f16d716e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With enabling FSP Notify Phase APIs, it has chance to issue a global
reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY
), which CSE already in idle mode and cause failure. For this reason we
should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select
SOC_INTEL_CSE_SEND_EOP_LATE instead.
BUG=b:261544011
BRANCH=firmware-brya-14505.B
TEST=tested and verified on Marasov, make sure this kind of global
reset can be executed successfully.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
On broadwell devices, coreboot currently disables and hides the ME PCI
interface by default, without any way to opt out of this behavior.
Add a Kconfig option to allow for leaving the ME PCI interface
enabled, but set the default to disabled as to leave the current
behavior unchanged.
Change-Id: If670d548c46834740f4e21bb2361b537807c32bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch drops the SoC specific implementation as DPTF driver can
now fillin those platform specific data using SoC specific macros.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If65976f15374ba2410b537b1646ce466ba02969b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This should only contain resources that the PCI domain uses. Stolen
memory prevents the PCI domain from allocating anything where it is.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1562396f0b747a81bbc584314956809bd3865ff9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66267
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9a4a05f9c764eecaac3d473ba612dca6cc81518f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove Top of Upper Usable DRAM Low from MCHC as it isn't needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifdd8c9ba61c5b1c6b154369413470e431ce8f5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current implementation of the MCRS had several issues with BARs
and MMCONF not being available:
[ 0.156231] pci 0000:00:02.0: BAR 2: assigned to efifb
[ 0.165302] pci 0000:00:18.2: can't claim BAR 0 [mem 0xddffc000-0xddffcfff 64bit]: no compatible bridge window
[ 0.192896] pci 0000:00:18.2: BAR 0: assigned [mem 0x280000000-0x280000fff 64bit]
...
[ 0.138300] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.138300] PCI: not using MMCONFIG
[ 0.148014] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.149674] [Firmware Info]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources
[ 0.149679] PCI: not using MMCONFIG
[ 0.155052] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge.
This new MCRS, tested on the Star Lite Mk IV, resolves these issues:
[ 0.158786] pci 0000:00:02.0: BAR 2: assigned to efifb
[ 0.197391] pci 0000:00:1f.1: BAR 0: assigned [mem 0x280000000-0x2800000ff 64bit]
...
[ 0.138460] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.138460] PCI: not using MMCONFIG
[ 0.150889] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.152548] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Different PCHs have different definitions for registers. Here create
a lbg folder and move lbg specific codes to this folder so that we
can add new PCH code under xeon_sp folder.
* Create lbg folder and move lbg specific codes from pch.c to soc_pch.c
under lbg folder.
* Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg
folder.
* Rename gpio.c to soc_gpio.c and move to lbg folder.
* Move pcr_ids.h to lbg folder.
* Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg
folder.
* Create and revise makefile for files under lbg folder.
TEST=Can boot into OS on OCP Delta Lake.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change provides config for devicetree to control ASPM per port
TEST=Build and Boot verified on google/rex
Port of 'commit 6e52c1da4a ("soc/intel/{adl,common}:
Add ASPM setting in pcie_rp_config)'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For LPC, set BIOS interface lock.
Also set the LPC BIOS control to match the SPI BIOS control settings.
BIOS control EISS and WPD are set when the BOOTMEDIA_SMM_BWP config
option is set.
Change-Id: I3e3edc63c0d43b11b0999239ea49304772a05275
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add system agent ID for RPL QDF#Q2MB/Q2PS
TEST=able to build coreboot successfully
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.
This patch is backported from
commit 8c46232005 (soc/intel/alderlake:
Disable L1 substates for PCIe compliance test mode).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This patch avoids hardcoding to the `use_eisa_hids` variable instead
relying on the SoC config to choose if the SoC platform supports
EISA HID.
If any SoC platform has the support then the `use_eisa_hids` variable
would be set to `true` based on the selection of `DPTF_USE_EISA_HID`
config.
Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA
IDs. If selected, the 7-character _HIDs will be emitted,
otherwise, it will use the "new" style, which are regular
8-character _HIDs.
Ideally, the platform prior to Tiger Lake would set `use_eisa_hids`
to `true` and platform posts that would set `use_eisa_hids` to
`false`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Volteer.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I111fa9b2672ad01268bb2620b47a53a7a5b00f3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71107
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibb31ab29c803dde70ef9ccf2b7c7c2ca0845b568
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71106
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Hatch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7a9218a41825d2fa40a1c1b96a333465b7f617c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71105
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Reef.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0ce956351afc06871c465b67f51cba8786ce52db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71104
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ied32eb301b0702ad7cf12b662886c9060415eb72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71103
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia4c3f1dbca2c0099cbf00137008c1aa1bcb196b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71125
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes the SoC specific callback code more readable by adding
`soc_` prefix into the `get_dptf_platform_info()`.
In nutshell this patch renames `get_dptf_platform_info()` to
`soc_get_dptf_platform_info()`.
TEST=Able to build Google/Rex without any compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309.
Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514
codecs to program the render and feedback slot numbers as appropriate.
TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify
audio functional with both Google project campfire drivers as well as
coolstar's AVS audio drivers.
Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Adapted from WIP (and abandoned) patch CB:25334, this patch:
1. Ensures SSP endpoint InstanceId is 0
2. Adds capability_size parameter at the end of the nhlt
3. Adsd more config_type enum values to accommodate feedback stream
4. Programs virtual_slot values for max98373, max98927,
and rt5514 nhlt files
5. Adds NHLT feedback_config parameters
Default feedback configs are added here to the max98373, max98927, and
rt5514 codecs; in a follow-on patch, these will be overridden at the
board level.
TEST=tested with subsequent patch
Change-Id: I59285e332de09bb448b0d67ad56c72a208588d47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
The patch rewrites `if` condition by connecting two different conditions
using the logical and(&&) operator without changing the semantics to
improve the code readability.
TEST=Build the code for Rex
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
This patch drops unused `dptf.asl` from the latest IA SoC platforms
as DPTF ACPI code generation is now relies on runtime aka SSDT
rather than having fixed dptf.asl files to include inside the
mainboard dsdt.asl.
TEST=Able to build Google/Kano without any compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE
and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the
same MSR that has been locked by another thread.
Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock
bit.
Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
As _Static_assert() is a compiler built-in, <assert.h> is not needed.
Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch fixes a hidden issue present inside FSP-S while coreboot
decides to skip performing MP initialization by overriding FSP-S UPDs
as below:
1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need
to use coreboot wrapper for performing any
operation over APs.
2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided
to skip FSP running CPU feature programming.
Unfortunately, the assumption of coreboot is not aligned with FSP when
it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of
the APs (Application Processors) upon passing `NULL` pointer to the
`CpuMpPpi` FSP-S UPD.
FSP-S creates its own infrastructure code after seeing the CpuMpPpi
UPD is set to `NULL`. FSP requires the CpuMpPei module, file name
`UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker`
to perform those additional initialization which is not relevant for
the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid
running CPU feature programming on APs).
Additionally, FSP-S binary size has increased by ~30KB (irrespective of
being compressed) with the inclusion of the CpuMpPei module, which is
eventually not meaningful for coreboot.
Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config
unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD
and avoid APs getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.
Ideally, FSP should have avoided all AP related operations when
coreboot requested FSP to skip MP init by overriding required UPDs.
TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on
Google/Redrix, Kano, Taeko devices with SkipMpInit=1.
Without this patch:
Here is the CPU AP logs coming from the EDK2 (open-source)
[UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the
CpuMpPpi UPD.
[SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6
[SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2
CpuMpPei.efi PROGRESS CODE: V03020002 I0
[SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
[SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE,
Peim notify entry point: 76FA0239
AP Loop Mode is 2
GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found.
CPU[0000]: Microcode revision = 00000000, expected = 00000000
[SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6
Does not find any stored CPU BIST information from PPI!
APICID - 0x00000000, BIST - 0x00000000
[SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97
[SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA
[SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A
PROGRESS CODE: V03020003 I0
With this patch:
No instance of `CpuMpPei` has been found in the AP UART log with FSP
debug enabled.
This patch is backported from
commit 8409f156d5 (soc/intel/alderlake:
Remove dependency of FSP-S CpuMpPei Module)
Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
The details about how the CPU multiprocessor init (MP) has migrated
from coreboot to FSP can be found in
https://doc.coreboot.org/soc/intel/mp_init/mp_init.html.
The major reason behind this migration is to support the Intel
proprietary and restricted CPU feature programming which can't be
performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part
of coreboot MP Init flow (prior to calling FSP-S). Hence, the new
flow introduced with Tiger Lake platform forced having monolithic
MP Init peformed by FSP (using coreboot MP PPI wrapper code).
The last 3-4 years of FSP doing MP Init has demonstrated ample
issues during platform bringup which is specific to UEFI MP Service
implementation and not relevant to open source coreboot. This new
flow makes the debug and validation aspect complicated where
any FSP MP Init code changes should have been validated with coreboot
MP PPI wrapper else might cause some failure, unfortunately,
the validation commitment has never been met, hence, issue debugging
is the only solution that remains in practice.
Most importantly, the restricted feature programming which demanded
closed source MP Init (for features like SGX and C6DRAM) has never
been enabled in coreboot (starting with Alder Lake, the SGX feature
has been dropped).
This patch attempts to decouple FSP-S doing MP Init from the rest
of the FSP-S silicon init and introduces 2nd MultiPhase SI init
which allows bootloader to perform the mandatory SoC programming
before FSP-S has done with PM programming (a.k.a set the reset CPL).
The core/uncore BWG suggests the minimum SoC programming before
BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2
to perform the required CPU programming before enabling the BIOS
Reset CPL.
This implementation would allow us to get rid of FSP running CPU
feature programming and additionally make several EDK2 MP service
modules optional (those are packed to create FSP-S blob).
In summary, this change would allow coreboot to utilize open source
MP init without running into FSP-S related code blocks.
Note: At present, Intel Meteor Lake FSP doesn't have support for
MultiPhase SI Init, Index 2 (submitted a FSP code changes over
chrome-internal to enable this feature to decouple MP Init from
FSP-S init).
This patch is backported from
commit b6c3a0325b (soc/intel/alderlake:
Implement MultiPhase SI Init Index 2 callback).
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Perform several thousands cycles of suspend test and power cycle
without running into any issue.
Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
