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coreboot/src/soc/intel
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Sean Rhodes a49cd32da0 soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of MMCONF 
The current implementation of the MCRS had several issues with BARs
and MMCONF not being available:

    [    0.156231] pci 0000:00:02.0: BAR 2: assigned to efifb
    [    0.165302] pci 0000:00:18.2: can't claim BAR 0 [mem 0xddffc000-0xddffcfff 64bit]: no compatible bridge window
    [    0.192896] pci 0000:00:18.2: BAR 0: assigned [mem 0x280000000-0x280000fff 64bit]
...
    [    0.138300] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.138300] PCI: not using MMCONFIG
    [    0.148014] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.149674] [Firmware Info]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources
    [    0.149679] PCI: not using MMCONFIG
    [    0.155052] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge.

This new MCRS, tested on the Star Lite Mk IV, resolves these issues:

    [    0.158786] pci 0000:00:02.0: BAR 2: assigned to efifb
    [    0.197391] pci 0000:00:1f.1: BAR 0: assigned [mem 0x280000000-0x2800000ff 64bit]
    ...
     [    0.138460] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.138460] PCI: not using MMCONFIG
    [    0.150889] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.152548] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-22 21:16:13 +00:00
..
alderlake soc/intel/alderlake: Add Raptor Lake device IDs 2022-12-22 18:47:50 +00:00
apollolake soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of MMCONF 2022-12-22 21:16:13 +00:00
baytrail tree: Replace LAnd(a,b) with ASL 2.0 syntax 2022-12-19 16:16:30 +00:00
braswell tree: Replace LAnd(a,b) with ASL 2.0 syntax 2022-12-19 16:16:30 +00:00
broadwell soc/intel/broadwell/early_init.c: Use {read,write}32p() 2022-12-13 14:31:11 +00:00
cannonlake soc/intel: Set use_eisa_hids based on DPTF_USE_EISA_HID config 2022-12-22 08:07:12 +00:00
common soc/intel/alderlake: Add Raptor Lake device IDs 2022-12-22 18:47:50 +00:00
denverton_ns soc/intel: Set IO APIC DMAR entry based on hw 2022-12-07 23:03:04 +00:00
elkhartlake soc/intel/elkhartlake: Add DPTF ACPI Device IDs into header file 2022-12-22 08:03:45 +00:00
icelake tree: Replace LAnd(a,b) with ASL 2.0 syntax 2022-12-19 16:16:30 +00:00
jasperlake soc/intel: Set use_eisa_hids based on DPTF_USE_EISA_HID config 2022-12-22 08:07:12 +00:00
meteorlake soc/intel/meteorlake: Add ASPM setting in pcie_rp_config 2022-12-22 18:54:18 +00:00
quark soc/intel/quark/Makefile.inc: Remove path to non-existent folder 2022-12-09 01:56:17 +00:00
skylake soc/intel/skl; mb/google/eve,poppy: Update NHLT methods 2022-12-21 14:00:13 +00:00
tigerlake soc/intel: Set use_eisa_hids based on DPTF_USE_EISA_HID config 2022-12-22 08:07:12 +00:00
xeon_sp soc/intel/xeon_sp: Move codes to support new PCH 2022-12-22 19:05:13 +00:00
Makefile.inc soc: Add SPDX license headers to Makefiles 2022-10-31 03:27:13 +00:00