Currently only SHA_GENERIC is used and does not need to be passed.
BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP and x86 verstage.
Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The SPI_RESTRICTED_CMD register is not a PCI configuration register. It
is memory mapped from the SPI bar.
Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243
rev 1.50
TEST=Compile tested only
Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PSP expects PSP L2 directory address relative to the start of the SPI
ROM. Also PSP does not expect BIOS L2 directory address since it is an
entry in PSP L2 directory. Update the configuration such that PSP
verstage passes the right address to PSP.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage passes the
address as expected by PSP.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8dc3aa4cb401d16a68da446f83eb9e68ee290fea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory
address relative to the start of the SPI ROM. Unfortunately there is
nothing in the EFS2 header to help identify such SoCs. Hence add a
config item to statically identify such SoCs.
Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in
the PSP L2 directory. Hence the address of BIOS L2 directory is not part
of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory
itself and does not expect PSP verstage to pass the address. Modify PSP
verstage to handle these updates.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP
L2 directory as expected.
Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSP supports mapping FCH UART and verstage logs are visible in console.
Hence pre-bootblock cbmem contents do not have to be dumped to console.
BUG=b:238937687
TEST=Build Skyrim BIOS image. Ensure that PSP verstage logs in CBMEM are
not dumped to console again during bootblock.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8336e372b894d8b2f9bbfb21ab15a78527dcc4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in
verstage.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP
verstage.
Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The APOB in sabrina is larger than in cezanne/picasso and no longer
fits in the previously allocated 64K space for it. Other symbols are
placed immediately after the APOB region and end up corrupting the APOB
data on sabrina.
Add a Kconfig option to specify the APOB size in DRAM to reserve enough
memory and increase the size for sabrina to 128K
TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN.
Build chausie and verify symbols do not overlap _apob region
BUG=b:224056176
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change is to allow AMD MP2 I2C OS driver to access
I2C0/1 devices when MP2 firmware is loaded.
Change-Id: Iaf25eb4dcf949e4b512ec0e86dbe5ccbc91c3d24
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65673
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the die() statement to a common place.
Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This allows the compiler to optimize out code called after run_ramstage.
Also remove some die() statements in soc code as run_ramstage already
has a die_with_postcode statement.
Change-Id: Id8b841712661d3257b0dc67b509f97bdc31fcf6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since there are many identifiers whose name contain "__unused" in
headers of musl libc, introducing a macro which expands "__unused" to
the source of a util may have disastrous effect during its compiling
under a musl-based platform.
However, it is hard to detect musl at build time as musl is notorious
for having explicitly been refusing to add a macro like "__MUSL__" to
announce its own presence.
Using __always_unused and __maybe_unused for everything may be a good
idea. This is how it works in the Linux kernel, so that would at least
make us match some other standard rather than doing our own thing
(especially since the other compiler.h shorthand macros are also
inspired by Linux).
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This makes it easier to have common code for MP init on AMD systems.
Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This avoids searching the HOB output multiple times when calling
smm_region().
Change-Id: Iad09c3aa3298745ba3ba7012e6bb8cfb8785d525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here.
BUG=b:218709292
TEST=Set serial soft fuse, boot to kernel, check logs
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This change adds new Rembrandt SoC support by defining it as base SoC
of sabrina as sabrina is derived from Rembrandt SoC.
All the needed changes for Rembrandt SoC will be applied under
SOC_AMD_REMBRANDT config.
Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reverting commit 1e25fd426a ("soc/amd/common/block/psp: introduce
AMD_SOC_SEPARATE_EFS_SECTION").
A better solution was used in commit c17330c1dd ("mb/amd/chausie: Add
EC blob into CBFS"), and this is no longer necessary.
TEST: Boot chausie
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I27a8622a1f0d871690b181a79adca225a20996ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Return the correct processor family code for smbios per System
Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0.
BUG=b:234409052
TEST=Boot chausie to chromeos and verify "dmidecode -t processor"
outputs the correct processor family.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most of the src/soc/Kconfig files are only there for AMD and Intel to
load the main SoC Kconfig files before any common files. That can be
done in src/Kconfig instead. Moving the loads to the lower level allows
the removal of all but the Intel soc/Kconfig file, which can be removed
in a follow-on patch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The common AMD ACPI GPIO access code is verified to be correct for
Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I834076c0a1d1784a272896f2d8f082ebfb86a383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The MCA banks were updated in commit 736d68c0b3 ("soc/amd/sabrina/mca:
update MCA bank names to match the hardware"), but seems that I forgot
to remove the TODO about checking if this is still correct for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd86113ccb9eeab704679afab0b985f9febed13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The common microcode update mechanism is verified to be correct and work
on Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5c41674299a829507438beb3ea597a71a0c5a972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Both UART and DMA MMIO regions for each UART are mapped by the
UEFI reference code, so do the same here.
Without these defined, UART-attached devices fail to correctly
initialize under Windows.
Change-Id: I0e1af9028c7c1746407e923cebe824a15aeb565e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65233
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 96f7b96866 (soc/amd/common/block/
cpu/: Make ucode update more generic) removed the code that used the
SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused
Kconfig option.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Without this, calls to i2c_link() and runtime i2c detection fails on
AMD common platform boards.
Test: Runtime i2c detection of correct touchpad model succeeds on
google/zork.
Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select
DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the
selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding
the Designware I2C bus ops handler in a subsequent commit.
Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The CPUID function to get the number of cores on a package is common
across multiple generations of AMD cpus.
Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The syscfg has to option to automatically mark the range between 4G and
TOM2, which contains DRAM, as WB. Making it generally not necessary to
allocate MTRRs for memory above 4G if no PCI BARs are placed up there.
Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
TSEG does not need to be aligned to 128KiB but to its size, as the MSR
works like an MTRR. 128KiB is a minimum TSEG size however.
TESTED on google/vilboz.
Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Sabrina only has 4 PCIe clock outputs with corresponding clock request
pins available, so only make those 4 configurable in devicetree and
disable the rest unconditionally.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Make the config file reflect reality instead of using the old cezanne
copy.
TEST=Build chausie
BUG=b:220848549
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I8362bc19875ae152e0deab7f64d5b1c50929b95b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify the config file, consumed by amdfwtool, to use "sabrina" and
"SBR" named files.
TEST=build chausie using updated amd_blobs
BUG=b:220848549
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ia993644e67d14792d753cc74a957529d15be18f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Sabrina APU has a maximum configuration of 4 physical cores with 2
threads each, so a total of 8 CPU cores.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MCA bank names were checked against PPR #57243 Rev 1.53.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1b947e686a0306d4468203103f91107c15ececc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina slightly changed the names of microcode patches. Adding a
wildcard to support the new name without breaking current builds that
are using the placeholder CZN binaries.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I86caf0ba5c15f64a9a1f0e76a3186919e5e761a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65069
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sabrina uses the SVI3 spec for VID tables which is incompatible with the
SVI2 spec used on PCO/CZN. Move the defines from common to soc and
update the decoding for sabrina.
See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables
TEST=timeless builds on mandolin/majolica for PCO/CZN
build chausie and verify pstate power is correct in ACPI tables
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I915e962f11615246690c6be1bee3533336a808f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
