According to the latest SPD parameters provided by the manufacturer,
combined with the document 8Gb_LPDDR4X_B_Die_component_Datasheet(S).pdf
we correct channelsPerDie, diesPerPackage, ranksPerChannel of SPD
for Nanya NT6AP1024F32BL-J1; merged the parameters into the BIOS and
flashed it into the machine. The machine can boot and read the normal
size of memory.
BUG=b.422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Use the dmidecode -t memory command to read the size of memory.
Output results：
awasuki-rev2 # dmidecode -t memory
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: None
Maximum Capacity: 64 GB
Error Information Handle: Not Provided
Number Of Devices: 4
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 32 bits
Data Width: 32 bits
Size: 8 GB
Form Factor: Unknown
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: LPDDR4
Type Detail: Synchronous
Speed: 2933 MT/s
Manufacturer: Unknown (b03)
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: NT6AP1024F32BL-J1
Rank: 2
Configured Memory Speed: 2933 MT/s
Minimum Voltage: 0.6 V
Maximum Voltage: 0.6 V
Configured Voltage: 0.6 V
Change-Id: I35823ce87b5d8d67894528e4a8781dd91247eb6c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88146
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds support for Zilia SDVB8D8A34XGCL3N3T LP4x chips.
Generatd SPD data with:
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
BRANCH=None
BUG=344482259
Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use the new unified version of the spd_gen tool to generate all LP4x and
DDR4 SPDs, storing them in a new spd/ directory. Storing them in a
common location allows platforms with the same SPD requirements to share
SPD files, reducing duplication compared to storing SPDs in soc/ and
mainboard/ directories.
For each memory technology there are multiple sets of SPDs. Each set
corresponds to a set of platforms with different SPD requirements, e.g.
due to different memory training code expectations. A manifest file
(platforms_manifest.generated.txt) lists the platform -> set mappings.
Commands used to generate SPDs:
cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \
spd/lp4x/memory_parts.json
cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \
spd/ddr4/memory_parts.json
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4
BUG=b:191776301
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
