- p4dpe sync with LNXI tree
* Make switching to fallback mode more robust
Added boot_countdown to count the number of times booting has failed.
* Added boot index to allow fully forcing the boot device with cmos options
* Added missing irqs to the mptable.
- p4dpr sync with LNXI tree
* Make switching to fallback mode more robust
Added boot_countdown to count the number of times booting has failed.
* Added boot index to allow fully forcing the boot device with cmos options
- tyan/guiness repair and update the Config file
- northbridge/amd/amd76x/
* Support for up to 4GB of ram.
* Correct handling of strange dimm sizes
- northbridge/intel/E7500
* Tunned settings for better memory performance
- northbridge/intel/E7501
* Fixed calculations based on a 100Mhz to use a 133Mhz clock.
* Replaced hard codes for the supermicro x5dpr
* Misc bug fixes
- src/ram/spotcheck.inc
* Removed someones temporary debugging code
- src/sdram/generci_zero_ecc_sdram.inc
* Handle addresses > 2GB
- src/southbridge/amd/amd768/
* Changed references to the amd766 to the amd768
* misc fixes
* Added a count to the failover code so we trigger fallback much less easily.
* more attempts to disable the amd768 watchdog...
* reset the board on a timeout reading from the smbus.
- src/southbridge/intel/82801
* added a count of boot failers so we trigger fallback mode much leass easily.
- Added motherboards p4dpeg2, x5dpr, s2466, s2469
src/ram/ramtest.inc{Add movnti ... }
src/southbridge/intel/82801ca/{sync the directory}
src/southbridge/intel/82870/{sync the directory}
src/southbridge/via/vt8231/southgbridge.c
- Transform intel_conf_xxx into pcibios_xxxx
src/southbridge/via/v82c686/southgbridge.c
- Transform intel_conf_xxx into pcibios_xxxx
src/winbond/w83627hf/Config
- Enable the hardware monitor
- Add support for turning on the power_led
util/config/NLBConfig.py
- Add support for object <something>.c
- Add support for object <something>.S
- recode how the list of source files is built up.
util/lb-dump/dump_lb_table.c
- Fix the memory size abreviations
- Support for remember our compile time environment
- Simple and always correct version of compute_ip_checksum
- Improve message strings in crt0.base
- Initial support for > 2G ram.
- Sizeram now returns a list of valid ranges of ram
- pci resource allocation now starts at 0xC0000000
- Update sizeram for every northbridge
- Misc cleanups.
- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
with addresses that are not cached so writing to ram does not work.
Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
the 16bit entry code in SMP.
- A small number of fixes for warnings
- VIA 686 cleanups from the A7M code (it now works in a different pci slot).
- Update of assembly printing routines to use the debug levels:
TTYS0_TX_CHAR now becomes CONSOLE_<LEVEL>_TX_CHAR.
It's more verbose but now the controls are the same as with the C code.
- Break off of loglevel.h from printk.h. loglevel.h is safe for both
the assembly routines and the C code to include.
- Next round of commits for the supermicro p4dc6
- SMP setup updates (Rons board is broken)
I now allow the other SMP processors to report their existence.
I really need to add a minimum time to run but that hasn't happened yet.
- SMP per motherboard table of apicids, as the assumption that they
would always be 0 & 1 with only two cpus fails.
- RDRAM setup updates. The code isn't done but it now works on more
than one board at a time.
- More cacheram work. Minor bug fixes and some macros to use it from C.
- Entry point changes so we no longer have to jump over our gdt.
- Added/Audited the cpufixup for the i786
- IDE intialization for the 82801 ich2 chip.
boot.c -- Modified to compile even with -fPIC
generic_sdram.inc -- split out generic_sdram_enable.inc -- Some chipsets
don't need that enable logic.
Added serial_fill_inbuf.c
Removed unused 440gx/param.h sis/630/param.h
Modified: make.base crt0.base ldscript.base mainboard/Config and NLBConfig.py
In NLBConfig.py added the directive mainboardinit (a variant of raminit.inc)
This allows us to remove hardcodes in crt0.S updated every mainboard/Config to
reflect the current state of the hardcodes, and the split of generic_sdram.inc
In crt0.S we should have the bare minimum code in assembly needed to get to C code.
mkrom is no longer needed.
