According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID
for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file.
[1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true
Test=Read and modify PCR registers of eSPI controller.
Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix always-true conditions to properly test whether a bit is set.
Change-Id: Ibfeafe222c0c2b39ced5b77f79ceb0c679a471b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 9a7fbbc98e.
SkipMbpHob UPD skips generation of MBP Hob within FSP. Skipping MBP
Hob generation also skips syncing correct version of chipset
data with CSE since FSP uses version information from MBP HOB.
In absence of MBP Hob, FSP is unable to get version information and
hence chipset data sync is skipped.
This creates an issue while platform tries to enter deeper sleep
states.
BUG=b:215448362
BRANCH=None
TEST= FSP can get version information from MBP HOB and chipset sync
is performed. It has been Verified using FSP debug logs on Brya
board.
Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Boards based on google/puff baseboard (hatch variant) use CSE LITE,
which utilizes RO and RW firmware. If the CSE does not switch to the
RW firmware, the HECI1 interface is disabled, and dependent drivers
(like SOF audio firmware) fail to load. Use the same logic as other
platforms utilizing CSE LITE (eg, TGL/JSL) to check if an ME RW
firmware update is available, and if not jump to the onboard RW
firmware.
Test: built/boot Manjaro 21.x on google/wyvern, verify CSE RW firmware
loaded via cbmem console, HECI1 interface is present vis lspci, and
the SOF DSP firmware is correctly loaded via dmesg.
Change-Id: I0ae21adde4a64bbcc5fa4fb144436a0430e92280
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61389
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is
memory mapped and ensures SkipCseRbp UPD is guarded against this config.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M
IDs in the current code. Hence rename those device IDs as ADL_M_N and
use them for Alder Lake-N platform.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
There may be occasions where an I2C device was initialized during
"early initialization," but when used again in ENV_PAYLOAD_LOADER
before resource allocation happens, it would currently return that it
has not been assigned a BAR. However, because of the early BAR
assigned to it, it should still be valid to use that until proper
resources have been assigned, therefore return any BAR that may have
been assigned to the device during early initialization.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8ab599199592a72ae96cd9f95accfaa0d84e66b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device
IDs.
Document Number: 619501, 645548
Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The headers added are generated as per Alder Lake N FSP v2503_00.
Changes include:
- Add all header files for Alder Lake N FSP.
- List of header files: FirmwareVersionInfoHob.h, FspmUpd.h, FspsUpd.h,
FspUpd.h, MemInfoHob.h
- Select FSP_HEADER_PATH
BUG=b:213828776
BRANCH=None
Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro to support mainboard
to lock NC and GPI_SCI pins as applicable.
BUG=b:216583542
TEST=build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61655
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c
flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to
indicate the port mapped to Type-C and sets Max TX and Pre-emp
settings. This is an extension to existing macro USB2_PORT_MAX.
The change is required to enable port reset event on a USB2 port.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state.
BUG=b:193287279
TEST=Build the code for Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61623
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements `cse_control_global_reset_lock()` as per ME BWG
(doc: 627331) recommendation.
It is recommended that BIOS should set this bit early on in the boot
sequence, and then clear it and set the CF9LOCK bit prior to loading
the OS in both an Intel CSME Enabled and a Intel CSME Disabled system.
Note: For CSE-Lite SKUs BIOS should set CF9LOCK bit unconditionally.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
- Optional feature to provide mechanism to skip _OFF and _On execution.
- It is used for the device to skip _OFF and _ON during device driver
reload.
- OFSK is used to skip _OFF Method at the end of device driver removal.
- ONSK is used to skip _ON Method at the beginning of driver loading.
- General flow use case:
1. Device driver is removed by 'rmmod' command.
2. Device _RST is called. _RST perform reset.
3. Device increments OFSK in _RST to skip the following _OFF invoked by
OSPM.
4. OSPM invokes _OFF at the end of driver removal.
5. _OFF sees OFSK and skips current execution and decrements OFSK so that
_OFF will be executed normally next time.
6. _OFF increments ONSK to skip the following _ON invoked by OSPM.
7. Device driver is reloaded by 'insmod/modprobe' command.
8. OSPM invokes _ON at the beginning of driver loading.
9. _ON sees ONSK and skip current execution and decrements ONSK so that
_ON will be executed normally next time.
- In normal case:
When suspend, OSPM invokes _OFF. Since OFSK is zero, the device goes
to deeper state as expected.
When resume, OSPM invokes _ON. Sinc ONSK is zero, the device goes
to active state as expected.
- Generated changes:
PowerResource (RTD3, 0x00, 0x0000)
Name (ONSK, Zero)
Name (OFSK, Zero)
...
Method (_ON, 0, Serialized) // _ON_: Power On
{
If ((ONSK == Zero))
{
...
}
Else
{
ONSK--
}
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
If ((OFSK == Zero))
{
...
}
Else
{
OFSK--
ONSK++
}
}
Test:
Enable and verify OFSK and ONSK Name objects and the if-condition logic
inside _OFF and _ON methods is added.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add L23 enter/exit, modPHY power gate, and source clock control methods.
DL23: method for L2/L3 entry.
L23D: method for L2/L3 exit.
PSD0: method for modPHY power gate.
SRCK: method for enabling/disable source clock.
These optional methods are to be used in the device ACPI to construct
flows with root port's power management functions.
Test:
Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch defines enum values for small and big cores and uses them
to indicate the big or small core.
TEST=Verify the build for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change is added to address the issue of USB3 ports downgrading to
high speed during low power modes and not returning back to super speed.
The patch enables port reset event on USB2 ports. This event is
is passed to USB3 upstream ports to upgrade back to super speed (USB3)
after a downgrade during low power state
BUG=b:193287279
TEST=Built coreboot on Gimble and tested type A pen drive detects as
super speed device
Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch removes `gpios_to_lock` lists and `soc_gpio_lock_config`
override function from Alder Lake SoC as the required config
(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) to perform GPIO PAD lock
configuration using SMM is not enabled.
Note: The current assumption is that the responsibility of locking the
sensitive GPIOs (from getting reprogrammed by OS or other SW) remains
with the mainboard.
BUG=b:208827718
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch removes mainboard capability to override GPIO PAD lock
configuration using `mb_gpio_lock_config` override function as the
variant GPIO pad configuration table is now capable of locking GPIO
PADs.
BUG=b:208827718
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3 => Set CSE device state to D0I3
- heci_set_to_d0i3 => Function sets D0I3 for all HECI devices
Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.
As per PCH EDS, the HECI device count for various SoCs are:
ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL => 1 (CSE)
SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3)
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch ensures PWRMBASE macro name and function to get PWRMBASE
address on APL SoC is aligned with other IA SoC.
PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS
read_pmc_mmio_bar() -> pmc_mmio_regs()
Additionally, make `pmc_mmio_regs` a public function for other IA common
code may need to get access to this function.
BUG=None
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The functionality of disabling HECI1 device has been moved from the
FSP to coreboot (using `DISABLE_HECI1_AT_PRE_BOOT` config), hence,
always set the `Heci1Disabled` UPD to `0`.
BUG=none
TEST=Boot to OS, verify HECI1 is disabled on hatch system
using coreboot when mainboard selects DISABLE_HECI1_AT_PRE_BOOT config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This option isn't meant to be assigned statically through devicetrees,
but at runtime according to some config mechanism. It works in
conjunction with the existing Kconfig option.
Change-Id: Ia760be61466bc6a0ec187746e6e32537029512b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Alder Lake to disable HECI1 device using PMC IPC.
Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Tiger Lake to disable HECI1 device using PMC IPC.
Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Select HECI_DISABLE_USING_SMM config for Jasper Lake to disable HECI1
device using the SBI msg in SMM.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Select HECI_DISABLE_USING_SMM config for Cannon Lake to disable HECI1
device using the SBI msg in SMM.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for
Apollo Lake to disable HECI1 device using PCR writes.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the
compilation failure.
Finally, rename heci_disable() function to heci1_disable() to make it
more meaningful.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch export cse_disable_mei_devices() function instead of marking
it static. Other IA common code may need to get access to this function
for making `heci1` device disable.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
New platforms have additional Primary to Sideband bridge besides the PCH
P2SB. This change puts the common functions into the P2SB library.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a devicetree option to disable SATA Aggressive Link Power
Management. ALPM is a method of saving power. The corresponding FSP-S
UPD parameter is enabled by default. It may be that this feature is
unwanted, for example for a real-time system. Therefore, allow to
disable ALPM using the devicetree.
Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated
from the FSP code.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alder Lake N has eMMC storage device. Select SOC_INTEL_COMMON_BLOCK_SCS
Kconfig for Alder Lake N.
Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Alder Lake N has eMMC storage device. Add PCR Port ID for it.
Reference: Alder Lake N platform EDS Doc# 645548.
Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO
IRQ routing information.
GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in
Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups.
GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO
communities 5-0 respectively.
BUG=b:213535859
Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe
coalescing logic where in case root port 0 is disabled, other enabled
root port is remapped to port 0.
coreboot handles this remapping scenarios for PCH and CPU PCIe root
ports and not for TBT root ports.
This patch uses the same function used for PCIe remapping to update
devicetree based on coalescing and SoC needs to pass correct function
number and number of slots.
BUG=b:210933428
BRANCH=None
TEST=Check if TBT remapping happens correctly and ACPI tables are
generated correctly.
Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
pcie_rp_update_devicetree function takes pcie_rp_group strcuture
as an argument and SoC code passes the parameter in this structure.
This pointer can be NULL and common code may try to dereference
this NULL pointer.
Also, group might have no data and SoC may pass this by indicating
group count as zero (For example, for CPU or TBT root ports).
These checks will prevent function from executing redundant code
and returning early from the call as it's not required.
BUG=b:210933428
BRANCH=None
TEST=check if function returns early for group count 0 and there is
no issue while booting board in case group count = 0.
Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds additional IGD device IDs as per document 638514.
BUG=b:216420554
TEST=coreboot is able to probe the IGD device during PCI enumeration.
Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch drops stale TODO comment about enabling eNEM on EHL.
eNEM is non-POR on the elkhartlake product.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
