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coreboot/src/soc/intel
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Subrata Banik 526cc3ed44 soc/intel/{adl, common}: Add routines into CSE IA-common code 
This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3    =>  Set CSE device state to D0I3
- heci_set_to_d0i3   =>  Function sets D0I3 for all HECI devices

Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.

As per PCH EDS, the HECI device count for various SoCs are:

ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL                     => 1 (CSE)
SKL/Xeon_SP             => 5 (CSE, IDE-R, KT, CSE2 and CSE3)

BUG=b:211954778
TEST=Able to build and boot Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-04 12:23:39 +00:00
..
alderlake soc/intel/{adl, common}: Add routines into CSE IA-common code 2022-02-04 12:23:39 +00:00
apollolake soc/intel/{adl, common}: Add routines into CSE IA-common code 2022-02-04 12:23:39 +00:00
baytrail src/{drivers,soc}: Fix some code indents 2022-01-28 15:10:46 +00:00
braswell src/{drivers,soc}: Fix some code indents 2022-01-28 15:10:46 +00:00
broadwell sb/intel: Use bool for PCIe coalescing option 2022-01-04 11:48:19 +00:00
cannonlake soc/intel/cannonlake: Forbid FSP from disabling HECI1 2022-02-03 13:48:56 +00:00
common soc/intel/{adl, common}: Add routines into CSE IA-common code 2022-02-04 12:23:39 +00:00
denverton_ns soc/intel/denverton_ns: Fix logging level 2022-01-26 21:24:51 +00:00
elkhartlake soc/intel/elkhartlake: Use SBI msg to disable HECI1 2022-02-02 07:10:21 +00:00
icelake soc/intel/common/cse: Rework heci_disable function 2022-02-02 07:09:28 +00:00
jasperlake soc/intel/jasperlake: Use SBI msg to disable HECI1 2022-02-02 07:38:01 +00:00
quark Rename ECAM-specific MMCONF Kconfigs 2021-11-10 17:24:16 +00:00
skylake soc/intel/{adl, common}: Add routines into CSE IA-common code 2022-02-04 12:23:39 +00:00
tigerlake soc/intel/tigerlake: Use PMC IPC to disable HECI1 2022-02-02 07:38:22 +00:00
xeon_sp soc/intel/{adl, common}: Add routines into CSE IA-common code 2022-02-04 12:23:39 +00:00
Kconfig
Makefile.inc soc/intel/common/cse: Add support for stitching CSE components 2021-10-19 16:09:08 +00:00