Add I2C chip initialization for the Galileo boards.
TEST=Build and run on Galileo Gen2
Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14829
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 15843bdad0)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346616
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the I2C driver.
TEST=Build and run on Galileo Gen2
Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14828
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit ac690b1e9b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346615
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set the base address and enable the GPIO and legacy GPIO controllers.
Call the mainboard routine to initialize the GPIO controllers.
TEST=Build and run on Galileo Gen2
Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14827
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 3f0fe68c4b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Kconfig to configure coreboot for a specific Galileo board.
Configure the GPIOs for the specific Galileo board.
TEST=Build and run on Galileo Gen2
Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14826
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 274d20a065)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
strlen(string) was on the negative side of the selection operator, the
side where string is NULL.
Change-Id: Ic421a5406ef788c504e30089daeba61a195457ae
Reported-by: Coverity Scan (CID 1355263)
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/14867
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
(cherry-picked from commit 0ba307f0fe)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346610
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This configures and enables SPI interface #5 used for EC
communications on Gru/Kevin.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the appropriate depthcharge change it is possible to trigger
booting Chrome OS from the SD card by pressing '^U' on Gru
keyboard at the right time.
Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346632
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
keyboard on Gru, which indicates that the EC interrupt GPIO is
properly configured. The rest of the pins will be verified later.
Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346631
This defines mux settings for the GPIO bank responsible for SPI
interface #5.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
communicate with the EC on gru: pressing Ctrl-U during boot
allows to start Chrome OS from the SD card.
Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346630
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
GPIOs are used in the upcoming patches.
Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346219
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Add register access routines for the GPIO and legacy GPIO controllers.
TEST=Build and run on Galileo Gen2
Change-Id: I0c023428f4784de9e025279480554b8ed134afca
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14825
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 083da160af)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346527
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Add LPC_DEV and LPC_FUNC symbols
TEST=Build and run on Galileo Gen2
Change-Id: I8485e2671af439f766228d4eaf9677c2ff8ff3f6
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14880
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 4c56a58f63)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346526
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Replace # define with #define
Align the right hand column to prepare for further expansion
TEST=Build and run on Galileo Gen2
Change-Id: Ie4d9fb56d52d7291be5523d31c1d3aa51f94dcd6
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14879
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 76684bf75b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346525
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This fixes compilation of coreboot on Glados
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
TEST=emerge-glados coreboot works again
BUG=none
Change-Id: Ibaae68192a3dc070c6ecf79223da4a1e1f18b352
Reviewed-on: https://chromium-review.googlesource.com/346198
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
The bootblock gets slightly too big, so adjust the space assigned to
it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=emerge-nyan coreboot works again.
Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c
Reviewed-on: https://chromium-review.googlesource.com/346492
Reviewed-by: Martin Roth <martinroth@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Simplify the union references to enable Coverity to properly process
the routine.
Found-by: Coverify CID 1349854
TEST=Build and run on Galileo Gen2
Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14870
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit d3989a26c1)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346524
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Coverity does not like the use of for/break, switch to using returns
instead.
Found-by: Coverity CID 1349855
TEST=Build and run on Galileo Gen2
Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14869
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 00c35c1a98)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346523
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add Ioh.h from EDK-II to enable easy comparisons between EDK-II and
coreboot implementations.
TEST=Build and run on Galileo Gen2
Change-Id: I9320101a4a2c16ed18f682f3d04623c54afb52fd
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14824
Original-Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
(cherry-picked from commit c1cbc605cd)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346522
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Don't allow an array index of 2 to be processed by the code referencing
the array.
Found-by: Coverity CID 1353337
TEST=None
Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14868
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 016d8f75d8)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346521
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Using a dedicated variable is slightly less readable and makes the code
less consistent, given that other test functions are called directly in
the if statements.
Change-Id: If52b2a4268acb1e2187574d15cc73a0c1d5fe9bb
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/14817
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 1811768c64)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346519
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add helper functions for generating some common objects:
acpigen_write_STA(status) will generate a status method that will
indicate the device status as provided:
Method (_STA) { Return (status) }
Full status byte configuration is possible and macros are provided for
the common status bytes used for generated code:
ACPI_STATUS_DEVICE_ALL_OFF = 0x0
ACPI_STATUS_DEVICE_ALL_ON = 0xF
acpigen_write_PRW() will generate a Power Resoruce for Wake that describes
the GPE that will wake a particular device:
Name (_PRW, Package (2) { wake, level }
Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14795
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit abe2de8854)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346518
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
In order to produce smaller AML and not rely on the caller to size the
output type appropriately add a helper function that will output an
appropriately sized integer.
To complete this also add helper functions for outputting the single
OpCode for Zero and One and Ones.
And finally add "name" variants of the helpers that will output a
complete sequence like "Name (_UID, Zero)".
Change-Id: I7ee4bc0a6347d15b8d49df357845a8bc2e517407
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14794
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit f7c3876c28)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346517
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add helper function to emit a string into the SSDT AML bytestream with a
NULL terminator. Also add a helper function to emit the string OpCode
followed by the string itself.
acpigen_emit_string(string) /* Raw string output */
acpigen_write_string(string) /* OpCode followed by raw string */
Change-Id: I4a3a8728066e0c41d7ad6429fad983e6ae6962fe
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 56b69aa9c7)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346516
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add helpers for writing word and dword values in acpigen and use them
throughout the file to clean things up:
acpigen_emit_word - write raw word
acpigen_emit_dword - write raw dword
acpigen_write_word - write word opcode and value
Change-Id: Ia758d4dd25d0ae5b31be7d51b33866dddd96a473
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14792
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 9ccae7558d)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346515
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add support for a basic generic device in the devicetree to bind to a
device that does not have a specific bus, but may need to be described
in tables for the operating system. For instance some chips may have
various GPIO connections that need described but do not fall under any
other device.
In order to support this export the basic 'scan_static_bus()' that can
be used in a device_operations->scan_bus() method to scan for the generic
devices.
It has been possible to get a semi-generic device by using a fake PNP
device, but that isn't really appropriate for many devices.
Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid
everything being rewritten. Clean up the local paths that leak into the
generated configs.
Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14789
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
(cherry-picked from commit 4650f5baff)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346514
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Use the second token for an i2c device entry in devicetree.cb to
indicate if it should use 10-bit addressing or 7-bit. The default if
not provided is to use 7-bit addressing, but it can be changed to
10-bit addressing with the .1 suffix. For example:
chip drivers/i2c/generic
device i2c 3a.1 on end
end
Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14788
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit b7ce5fe311)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346513
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
This adds the initial scaffolding for the reef reference board.
One big thing missing is the GPIO configuration.
Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f
Original-Signed-off-by: Aaron Durbni <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14798
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
(cherry-picked from commit e065bb43d7)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346510
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.
Change-Id: I686eb3097c33399a3b94af89237f7fe1b2d34c2f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14790
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
(cherry-picked from commit fc2e7413b3)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346469
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I6b345670db7df652b8b712b721dfe2905373e0d5
Original-Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-on: https://review.coreboot.org/14630
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: York Yang <york.yang@intel.com>
(cherry-picked from commit 0b4db13994)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346468
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I1bd33e423b0fcb69597e001b61c6ea916f5fe44a
Original-Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-on: https://review.coreboot.org/14622
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
(cherry-picked from commit 1eaf58be2c)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346467
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
PCI device ID of this mini-PCI-e WLAN card is 8086:088e.
With this card inserted on pcengines/apu1 mini-PCI-e slot J17,
system halts late in ramstage, in agesawrapper AMD_INIT_MID.
Offending operation is enabling PCIe ASPM L0s and L1 for the card.
That is, writing PCIe capability block Link Control [1:0] = 11b
in the card's configuration space. AGESA already has a blacklist
for the purpose of masking such unstable ASPM implementations.
Change-Id: I9623699c4ee68e5cdc244b87faf92303b01c4823
Original-Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/8496
Original-Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit a53977e232)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346466
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
In order for apollolake mainboards to utilize the common GPIO API
it actually needs to be implemented.
Change-Id: I41de8d5d9f3c39e7e796eae73b01cb29e9c01347
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14797
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
(cherry-picked from commit fc6a9f2c20)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346463
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
In order to allow using the same C source to be compiled
for multiple stages (with #if/#endif guards) one needs the
necessary function delcarations. Therefore, remove the
guards.
Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14796
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
(cherry-picked from commit c10ac755f0)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346462
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Update the DDR config and DRAM driver to allow running at up to
928MHz. Kevin config/clock rate are not being changed, but Gru now
runs at 928 MHz.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru,
Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343984
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346299
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Trybot-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
This patch enable eDP display by,
o. set HPD pinmux, backligh, vdd for eDP
o. set vop mode
o. enable VGA configs for edid
BRANCH=none
BUG=chrome-os-partner:51537
TEST=the dev screen shown on kevin board
Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340026
Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/346296
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Trybot-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
This patch add functions to init display. To setup display,
initialize the eDP and read EDID, basing on which we then
set the clock for VOP, and finally enable VOP and backlight.
For a mainboard, it should set the vop_id, vop_mode and
framebuffer_bits_per_pixel in devicetree.cb.
For VOP_MODE_AUTO_DETECT, it will try eDP first and then
HDMI(which is not supported yet).
BRANCH=none
BUG=chrome-os-partner:51537
TEST=test with the other patch
Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/342336
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346295
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Trybot-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
If booting from sdcard/usb, kernel can't recognize the
/dev/mmcblk0.
Before kernel find it's root cause, we add this workaround
patch to enable clk for emmc.
BRANCH=none
BUG=chrome-os-partner:52873
TEST=boot from sdcard and check the /dev/mmcblk0 exists
Change-Id: I88a9cc2e3ea5a56aadfdbd94ef910daaf92a7eb7
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/341632
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346294
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Trybot-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz,
that is GPLL(594MHz) divided by 3.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard
TEST=LoadKernel faster, more than twice as I measured manually.
Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/339152
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346293
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Trybot-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Allow EC to send an interrupt using ACPI SMI when a MKBP event
is available. This will be used by the sensor stack.
Update all ACPI branch except those without sensors with:
for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+
| cut -d '/' -f 2 | grep -v -e cyan -e lars); do
echo $i
cd $i
git diff ../lars/ec.h | patch -p 5
cd -
done
BUG=b:27849483
BRANCH=none
TEST=Compile on Samus. Tested in Cyan branch.
Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342364
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346292
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Trybot-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Enable users to set the EC_EXTERNAL_FIRMWARE config flag, and actively
ignore anything related to EC firmware board names if enabled.
BUG=none
BRANCH=none
CQ-DEPEND=CL:344540
TEST=emerge-samus coreboot works
Change-Id: I39c3038d059ec3d7710b864061fcf83b8d6d4d13
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/345584
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Trybot-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
For proper interface operation the drive strength on all pins is set
to 8 mA and all pull ups/pull downs disabled, this matches the current
kernel configuration.
BRANCH=none
BUG=chrome-os-partner:53257
TEST=it is possible to boot Chrome OS on Gru from various micro SD
cards which were failing to boot before.
Change-Id: I5180537d3ceb74a9a2f7b3982ca94d3e2daf0369
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344491
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The code needs to be able to set drive strength for the pins used for
SDMMC0 interface. This patch adds the definitions for the two
registers, as per page 378 of the RK3399 TRM Part 1.
Instead of calculation of the reserved range size just use known
offsets of the registers included in the structure.
BRANCH=none
BUG=chrome-os-partner:53257
TEST=with the upcoming driver change it is possible to boot chrome OS
on Gru from various micro SD cards which were failing before.
Change-Id: Ibe7584e77b446435ab1264dcf8fc8bfe0c50438e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344490
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The only outlier at this time is Kevin rev 0, treat it specially, the
rest of the targets use the same GPIO.
BRANCH=none
BUG=none
TEST=gru still boots off SD card just fine
Change-Id: Ic5183f08dd1119f9588f243bd9e9c080d84687f9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344151
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
now we use 4GB sdram on gru board, enable it.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot from kevin board
Change-Id: I26f77ff4ad9b2aa35ab5ff50f23984796f4f06bc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/342585
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
improve rk3399 sdram drvier, so we can support DDR3,
and check the cs training result, so we make sdram
work more stable.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot from kevin, do memtester in kernel and pass
Change-Id: Id385f1343804a829b6589f89f4cfbb6565d41417
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342664
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
This patch configures clock for tsadc and then
makes it in automatic mode to generate TSHUT when
CPU temperature is higer than 120 degree Celsius.
BRANCH=none
BUG=chrome-os-partner:52382,chrome-os-partner:51537
TEST=Set a lower tshut threshold(45C), run coreboot and check
that coreboot reboot again and again.
Change-Id: Iffe54d3b09080d0f1ff31e8b3020d69510f07c95
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/342797
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shelley Chen <shchen@chromium.org>
The tsadc of rk3288 and rk3399 are similar but not enough
to share the same common driver, and we also decide to add a
polarity setting for mainboards on rk3399 tsadc header.
So we'd better split the tsadc header for each SoC.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=build veyron_jerry
Change-Id: I629599f9e30d863cabf764e1372c38f0f39d5480
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/342796
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
