The end of firmware notification is currently not being tracked
so it's hard to get good data on how long it takes. Update the
code to provide timestamp data as well as post codes.
BUG=chrome-os-partner:56656
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17373
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2
Reviewed-on: https://chromium-review.googlesource.com/411438
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since tlcl library is used other than just vboot driver, ensure that the
library is initialized only once per stage.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified in recovery mode on reef, tlcl library is initialized only
once in romstage.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I6245fe9ed34f5c174341b7eea8db456b45113287
Reviewed-on: https://chromium-review.googlesource.com/411434
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wacom I2C driver can be used by devices other than
touchscreen. e.g. digitizer. So there is no need to name the driver
with touchscreen specific attributes. Only a separate descriptor name
is required that needs to be set by mainboard correctly.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Compiles successfully.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194
Reviewed-on: https://chromium-review.googlesource.com/410117
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This space is read/updated only in recovery mode.
1. During read phase, verify if the hash of MRC data read from
RECOVERY_MRC_CACHE matches the hash stored in TPM.
2. During update phase, calculate hash of training data returned by MRC
and save it in TPM.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified MRC data hash comparison and update operation on reef.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifcbbf1bd22033767625ec55b659e05fa7a7afc16
Reviewed-on: https://chromium-review.googlesource.com/410115
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or
RECOVERY_MRC_CACHE based on the boot mode.
- If normal mode boot, use RW_MRC_CACHE, if available.
- If recovery mode boot:
- Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is
requested explicity with retrain memory request.
- Use RECOVERY_MRC_CACHE otherwise.
2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot
modes. Check if both are present under one unified region and protect
that region as a whole. Else try protecting individual regions.
3. Update training data in appropriate cache:
- Use RW_MRC_CACHE if normal mode.
- Use RECOVERY_MRC_CACHE if present in recovery mode. Else use
RW_MRC_CACHE.
4. Add proper debug logs to indicate which training data cache is used
at any point.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified that correct cache is used in both normal and recovery
mode on reef.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17242
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3
Reviewed-on: https://chromium-review.googlesource.com/410099
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
WACOM request to add a new identifier `WCOMNTN2`,
and use that for the board Pyro with all LCD combinations.
BRANCH=master
BUG=chrome-os-partner:58093
TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage
Signed-off-by: Janice Li <janice.li@quantatw.com>
Reviewed-on: https://review.coreboot.org/17257
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307
Reviewed-on: https://chromium-review.googlesource.com/410072
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Increase the IRQ timeout to prevent issues if there is a delay
in the TPM responding to a command. Split the no-IRQ case out
so it doesn't suffer unnecessarily.
BUG=chrome-os-partner:59191
BRANCH=None
TEST=suspend/resume testing on eve board
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17204
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I1ea7859bc7a056a450b2b0ee32153ae43ee8699f
Reviewed-on: https://chromium-review.googlesource.com/408971
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All current implementations of ramstage_cache_invalid() were just
resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE
Kconfig option. Move that behavior to a single implementation
within prog_loaders.c which removes duplication.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17184
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e
Reviewed-on: https://chromium-review.googlesource.com/406946
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Export i2c_generic_fill_ssdt to allow other device-specific i2c
drivers to share and re-use the same code for generating AML code for
SSDT. In order to achieve this, following changes are required:
a. Add macro I2C_GENERIC_CONFIG that defines a structure with all
generic i2c device-tree properties. This macro should be placed by the
using driver at the start of its config structure.
b. Accept a callback function to add any device specific information to
SSDT. If generic driver is used directly by a device, callback would be
NULL. Other devices using a separate i2c driver can provide a callback
to add any properties to SSDT.
2. Allow device to provide _CID.
BUG=chrome-os-partner:57846
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17089
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4
Reviewed-on: https://chromium-review.googlesource.com/402514
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support to allow a device to define PowerResource in its SSDT AML
code. PowerResouce ACPI generation expects SoC to define the
callbacks for generating AML code for GPIO manipulation.
Device requiring PowerResource needs to define following parameters:
1. Reset GPIO - Optional, GPIO to put device into reset or take it out
of reset.
2. Reset delay - Delay after reset GPIO is de-asserted (default 0).
3. Enable GPIO - Optional, GPIO to enabled device.
4. Enable delay - Delay after enable GPIO is asserted (default 0).
BUG=chrome-os-partner:55988
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17081
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad
Reviewed-on: https://chromium-review.googlesource.com/402510
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When compiling a non-x86 platform with DRIVERS_INTEL_WIFI enabled,
we get the build error:
src/drivers/intel/wifi/wifi.c:17:30: fatal error:
arch/acpi_device.h: No such file or directory
acpi_device.h only exists in the x86 architecture directory.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16906
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Change-Id: Id0e29558336bf44e638cfcb97c22f31683ea4ec7
Reviewed-on: https://chromium-review.googlesource.com/396228
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables stage cache to save ~40ms during S3 resume.
It saves ramstage in the stage cache and restores it on resume
so that ramstage does not have to reinitialize during the
resume flow. Stage cache functionality is added to postcar stage
since ramstage is called from postcar.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for Reef and tested ramstage being cached
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16833
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72
Reviewed-on: https://chromium-review.googlesource.com/396161
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of hard-coding the polarity of the GPIO to active high/low,
accept it as a parameter in devicetree. This polarity can then be used
while calling into acpi_dp_add_gpio to determine the active low status
correctly.
BUG=chrome-os-partner:55988
BRANCH=None
TEST=Verified that correct polarity is set for reset-gpio on reef.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919
Reviewed-on: https://chromium-review.googlesource.com/396152
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the setup of the IRQ status handler so it will be set up properly
before the early probe happens.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16861
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I4380af1233d2a252899459635a3cb69ca196088d
Reviewed-on: https://chromium-review.googlesource.com/393296
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Kconfig hex values don't need to be in quotes, and should start with
'0x'. If the default value isn't set this way, Kconfig will add the
0x to the start, and the entry can be added unnecessarily to the
defconfig since it's "different" than what was set by the default.
A check for this has been added to the Kconfig lint tool.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16834
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I86f37340682771700011b6285e4b4af41b7e9968
Reviewed-on: https://chromium-review.googlesource.com/391938
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A copy of our uart8250io driver sneaked in with Broadwell-DE support.
The only difference is the lack of initialization (due to FSP handling
that).
TEST=manually compared resulting object files
BUG=None
BRANCH=None
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16786
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I09be10b76c76c1306ad2c8db8fb07794dde1b0f2
Reviewed-on: https://chromium-review.googlesource.com/391790
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a config option to the generic I2C device driver to indicate to
the OS that this device should be probed before being added.
This can be used to provide ACPI device instantiations to devices that
may not actually exist on the board. For example, if multiple trackpad
vendors are supported on the same board they can both be described in
ACPI and the OS will probe the address and load the driver only if the
device responds to the probe at that address.
BUG=chrome-os-partner:57686
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16742
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I22cffb4b15f25d97dfd37dc58bca315f57bafc59
Reviewed-on: https://chromium-review.googlesource.com/390892
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The VBT id string is 20 characters long.
If the string is shorter than 20 it needs spaces at the end.
This change is cosmetic as all strings were padded by hand.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16739
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Id6439f1d3dbd09319ee99ce9d15dbc3bcead1f53
Reviewed-on: https://chromium-review.googlesource.com/390400
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
UX Doc = go/gale-hw-ui
This color wasn't changed earlier as the change wasn't done in
the OS also. However, since we cannot change this later in FW
(but OS can change anytime), I am making this change after discussing
with the UX team.
BUG=b:31501528, b:31633562
TEST=Change the device state to 'recovery mode' to observe the new
color.
BRANCH=none
Change-Id: I88768b94cf91804a6005e44b1a168e059698ec4b
Signed-off-by: Suresh Rajashekara <sureshraj@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388206
Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org>
Tested-by: Suresh Rajashekara <sureshraj@chromium.org>
Reviewed-by: Christopher Book <cbook@chromium.org>
Reviewed-by: Kan Yan <kyan@google.com>
Support reading the ACPI GPE status (on x86) to determine when
the cr50 is ready to return response data or is done processing
written data. If the interrupt is not defined by Kconfig then
it will continue to use the safe delay.
This was tested with reef hardware and a modified cr50 image
that generates interrupts at the intended points.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16672
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ic8f805159650c45382cacac8840450a1f8b4d7a1
Reviewed-on: https://chromium-review.googlesource.com/388312
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Unify the function names to be consistent throughout the driver
and improve the handling while waiting for data available and
data expected flags from the TPM.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16668
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie2dfb7ede1bcda0e77070df945c47c1428115907
Reviewed-on: https://chromium-review.googlesource.com/388308
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rename the low-level functions from iic_tpm_read/write to
cr50_i2c_read/write to better match the driver name, and pass in the
tpm_chip structure to the low-level read/write functions as it will
be needed in future changes.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16666
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I826a7f024f8d137453af86ba920e0a3a734f7349
Reviewed-on: https://chromium-review.googlesource.com/388306
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use two different timeouts in the driver. The 2ms timeout is needed
to be safe for cr50 to cover the extended timeout that is seen with
some commands. The other at 2 seconds which is a TPM spec timeout.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16665
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia396fc48b8fe6e56e7071db9d74561de02b5b50e
Reviewed-on: https://chromium-review.googlesource.com/388305
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reduce the static buffer size from the generic default 1260
down to 64 to match the max FIFO size for the cr50 hardware
and reduce the footprint of the driver.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I6f9f71d501b60299edad4b16cc553a85391a1866
Reviewed-on: https://chromium-review.googlesource.com/388304
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Originally I thought it would be cleaner to keep this code in one
place, but as things continue to diverge it ends up being easier
to split this into its own driver. This way the different drivers
in coreboot, depthcharge, and the kernel, can all be standalone
and if one is changed it is easier to modify the others.
This change splits out the cr50 driver and brings along the basic
elements from the existing driver with no real change in
functionality. The following commits will modify the code to make
it consistent so it can all be shared with depthcharge and the
linux kernel drivers.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16663
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I3b62b680773d23cc5a7d2217b9754c6c28bccfa7
Reviewed-on: https://chromium-review.googlesource.com/388303
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the common enums and variables to tpm.h so it can be
used by multiple drivers.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16662
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie749f13562be753293448fee2c2d643797bf8049
Reviewed-on: https://chromium-review.googlesource.com/388302
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove fsp1.1 driver code that adds vbt.bin & use soc/intel/common
instead to add vbt.bin in cbfs.
Also, VBT blob is added to CBFS as RAW type hence when walking the
CBFS to find vbt.bin, search with type as RAW.
BUG=None
BRANCH=None
TEST=None
Change-Id: Iad0cfae45889b8d209840f8627ecdad794bf7e51
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388114
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Colors and patters defined by UX team can be found at go/gale-hw-ui
BUG=b:31501528
TEST=Move the device to different states in FW using rec and dev
button and verify the colors
BRANCH=None
Change-Id: I95ab1fa59b483396ff1498a28f1ee98ac08d02d7
Signed-off-by: Suresh Rajashekara <sureshraj@google.com>
Reviewed-on: https://chromium-review.googlesource.com/387258
Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org>
Tested-by: Suresh Rajashekara <sureshraj@chromium.org>
Reviewed-by: Christopher Book <cbook@chromium.org>
Reviewed-by: Kan Yan <kyan@google.com>
If FSP_M_XIP is selected, then relocate FSP-M binary
while adding it in CBFS so that it can be executed in place.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f
Reviewed-on: https://chromium-review.googlesource.com/385899
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The TPM driver was largely ignoring the meaning of the command
ready bit in the status register, instead just arbitrarily
sending it at the end of every receive transaction.
Instead of doing this have the command ready bit be set at the
start of a transaction, and only clear it at the end of a
transaction if it is still set, in case of failure.
Also the cr50 function to wait for status and burst count was
not waiting the full 2s that the existing driver does so that
value is increased. Also, during the probe routine a delay is
inserted after each status register read to ensure the TPM has
time to actually start up.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2
Reviewed-on: https://chromium-review.googlesource.com/385897
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The early TPM probe was done directly in tis.c ignoring the lower
layer that provides appropriate access to the chip. Move this into
a tpm_vendor_probe() function so it can use iic_tpm_read() with all
of the built-in delays and semantics instead of calling i2c_readb()
directly from the wrong layer.
This fixes early init failures that were seen with the cr50 i2c tpm
on the reef mainboard.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I9bb3b820d10f6e2ea24c57b90cf0edc813cdc7e0
Reviewed-on: https://chromium-review.googlesource.com/382721
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the TPM completely fails to respond then the vendor structure may not
have assigned handlers yet, so catch that case and return error so the
boot can continue to recovery mode instead of asserting over and over.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16416
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: If3a11567df89bc73b4d4878bf89d877974044f34
Reviewed-on: https://chromium-review.googlesource.com/382079
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add code to generate an ACPI descriptor for an I2C TPM based
on the device as described in devicetree.cb.
This currently requires the devicetree to provide the HID,
since we don't currently talk to the TPM in ramstage and I
didn't want to add yet another init path for it here.
This was tested on a reef board to ensure that the device
is described properly in the SSDT.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16397
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I43d7f6192f48e99a4074baa4e52f0a9ee554a250
Reviewed-on: https://chromium-review.googlesource.com/382077
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for the cr50 TPM used in apollolake chromebooks.
This requires custom handling due to chip limitations, which
may be revisited but are needed to get things working today.
- timeouts need to be longer
- must use the older style write+wait+read read protocol
- all 4 bytes of status register must be read at once
- same limitation applies when reading burst count from status reg
- burst count max is 63 bytes, and burst count behaves
slightly differently than other I2C TPMs
- TPM expects the host to drain the full burst count (63 bytes)
from the FIFO on a read
Luckily the existing driver provides most abstraction needed to
make this work seamlessly. To maximize code re-use the support
for cr50 is added directly instead of as a separate driver and the
style is kept similar to the rest of the driver code.
This was tested with the cr50 TPM on a reef board with vboot
use of TPM for secdata storage and factory initialization.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16396
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Change-Id: I9b0bc282e41e779da8bf9184be0a11649735a101
Reviewed-on: https://chromium-review.googlesource.com/382076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Allow the sleep durations used by the driver to be set by the
specific chip so they can be tuned appropriately.
Since we need to read the chip id to know the values use very
conservative defaults for the first command and then set it
to the current values by default.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16395
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ic64159328b18a1471eb06fa8b52b589eec1e1ca2
Reviewed-on: https://chromium-review.googlesource.com/382075
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use CAR accessors where needed for accessing static data.
In some cases this required some minor restructuring to pass
in a variable instead of use a global one.
For the tpm_vendor_init the structure no longer has useful
defaults, which nobody was depending on anyway. This now
requires the caller to provide a non-zero address.
Tested by enabling I2C TPM on reef and compiling successfully.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16394
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I8e02fbcebf5fe10c4122632eda1c48b247478289
Reviewed-on: https://chromium-review.googlesource.com/382074
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SPI read speed directly impacts boot time and we do quite a lot of
reading.
Add a way to easily find out the speed of SPI flash reads within
coreboot.
Write speed is less important since there are very few writes and they
are small.
BUG=chrome-os-partner:56556
BRANCH=none
TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages:
read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps
Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376944
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Simon Glass <sjg@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
FSP header files should be located in vendorcode, not soc directory.
This patch includes changes any references to the old location to
the new location.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I44270392617418ec1b9dec15ee187863f2503341
Reviewed-on: https://chromium-review.googlesource.com/381008
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
