UPSTREAM: Kconfig: Prefix hex defaults with 0x

Because these variables had "non-hexidecimal" defaults, they
were updated by kconfig when writing defconfig files.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16827
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873
Reviewed-on: https://chromium-review.googlesource.com/391792
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/drivers/intel/fsp1_1/Kconfig

@@ -34,13 +34,13 @@ config HAVE_FSP_BIN
 
 config CPU_MICROCODE_CBFS_LEN
 	hex "Microcode update region length in bytes"
-	default 0
+	default 0x0
 	help
 	  The length in bytes of the microcode update region.
 
 config CPU_MICROCODE_CBFS_LOC
 	hex "Microcode update base address in CBFS"
-	default 0
+	default 0x0
 	help
 	  The location (base address) in CBFS that contains the microcode update
 	  binary.

src/drivers/uart/Kconfig

@@ -69,7 +69,7 @@ config UART_USE_REFCLK_AS_INPUT_CLOCK
 
 config UART_PCI_ADDR
 	hex "UART's PCI bus, device, function address"
-	default 0
+	default 0x0
 	help
 	  Specify zero if the UART is connected to another bus type.
 	  For PCI based UARTs, build the value as:

src/mainboard/google/daisy/Kconfig

@@ -49,7 +49,7 @@ config DRAM_SIZE_MB
 
 config EC_GOOGLE_CHROMEEC_I2C_BUS
 	hex
-	default 4
+	default 0x4
 
 config UART_FOR_CONSOLE
 	int

src/mainboard/google/smaug/Kconfig

@@ -85,7 +85,7 @@ config DRIVER_TPM_I2C_ADDR
 
 config EC_GOOGLE_CHROMEEC_I2C_BUS
 	hex
-	default 1
+	default 0x1
 
 config EC_GOOGLE_CHROMEEC_BOARDNAME
 	string