The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0409e8e9d6a203254a9f9b749de5cab70dfc842
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4d7abc0d4
Original-Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488047
The console log level variable doesn't really rely on ROMSTAGE_CONST
proper. Instead, the mutability of the variable is based on the current
implementation of ROMSTAGE_CONST (__PRE_RAM__). As such directly
use that logic for the code. In addition, refactor the code to let
the compiler and linker optimize out accesses instead of using
the pre-processor.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie38d062b92b9bcd7bf7faf88a9495c52c0d5488d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4003950881
Original-Change-Id: I44bcc409266ef52b9be29f75efde73a6707a53f4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/488046
The ramstage-c-ccopts variable needs to be double dereferenced
for the cbfs-files-processor-struct handler so all the ccopts
are included since the ramstage-c-ccopts is fully constructed
later by another function. Without this not all the flags
are present on the command line.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic3d0b9f7ddf2cd0d3b542bd35a2d7e209a77c364
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42bcd13c75
Original-Change-Id: I5425b3c1f23d767c61f654dd287584403f85d719
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19380
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/488045
Delete the write to PM register 0xee. This register is not
listed in the current BKDG and S4 is not currently supported
on this APU.
NDA document #47517 "A55/.../A85X fusion Controller Hub Register
Reference Guide" provides some clues on the intent of this write.
This register has always been observed to power on with a value
of 0x08 so the write has no effect.
This should be revisited again when SMI and PSP fully implement
the support required for S3.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7c01148c21a07b51848f59e85161cb30450fa7a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e438af995
Original-Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18494
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486780
Create new functions similar to read and write of other sizes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I02df458e0af93e614768636ead2ab693ccbca90a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: efd077ac52
Original-Change-Id: I35a08c498f25227233604c65c45b73b1c44fae1f
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19394
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486779
The SD/MMC support is broken into several pieces. There are three main
data structures:
* sdhci_ctrlr - This is SDHCI controller specific and defined in
include/device/sdhci.h
* sd_mmc_ctrlr - This contains generic controller management data and
defined in include/device/sd_mmc_ctrlr.h
* storage_media - This contains the flash storage device management data
and is defined in include/device/storage.h
The SD/MMC driver consists of several components:
* SDHCI controller code
* bouncebuf.c
* bouncebuf.h
* pci_sdhci.c
* sdhci.c
* sdhci.h
* sdhci_adma.c
* sdhci_display.c
* Flash storage device support
* mmc.c
* mmc.h
* sd.c
* sd_mmc.c
* sd_mmc.h
* storage.c
* storage.h
* storage_erase.c
* storage_write.c
Kconfig values enable various portions of the controller and storage
drivers to be built to reduce the overall size of what is included in
the final image.
Full read/write/erase operations are provided for those platforms which
want to take advantage. It is also possible to build the driver to
perform initialization only. By default, this driver is not included in
any platform, platforms must specifically select DRIVERS_STORAGE to add
the SD/MMC support.
After this patch is reviewed and merged, there are some additional
patches:
* Common CAR storage area - Use a predefined region of CAR to pass data
structures between bootblock through to romstage. This allows early
stages to preform the SD/MMC device initialization and later stages
to use the SD/MMC device without further initialization. The example
code initializes the SD/MMC device in bootblock and uses the SD/MMC
device in romstage without further initialization.
* CBMEM ID - Add a CBMEM ID value for the data structures so that they
may be passed from romstage to ramstage and eventually the payload.
The example uses the SD/MMC device in ramstage without further
initialization.
* Move the SD/MMC driver into commonlib
* Have libpayload build the SD/MMC driver from commonlib. The intent
is to pass the controller state to libpayload so that the SD/MMC
device can be used without further initialization.
* On some platforms, have depthcharge use the commonlib SD/MMC driver
History:
Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot
and make the following changes:
* Removed #include "config.h" from mmc.c, allow the lint tests to pass.
* Move include files from drivers/storage into include/device.
* Rename mmc.h to storage.h.
* Add the Kconfig and Makefile and make edits to get the code to build.
* Add support to initialize a PCI controller.
* Fix formatting issues detected by checkpatch.
* Fix data flow issues detected by checkpatch.
* Add the missing voltage (MMC_VDD_35_36) into the voltage mask.
* Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*.
* Replace printf with sd_mmc_error.
* Add sdhc_debug, sdhc_trace and sd_error macros.
* Add Kconfig values to enable storage device debugging and tracing.
* Add tracing and debug support to the SDHCI driver.
* Allow SOC to override more controller features.
* Split out ADMA support.
* Move 1V8 support into SOC routine.
* Move HS400 support into SOC routine.
* Rework clock handling.
* Change all controller references to use ctrlr.
* Update the voltage handling.
* Update modes of operation.
* Move DMA fields into MmcCtrlr.
* Update bus width support.
* Change MMC_TIMING_* to BUS_TIMING_*.
* Rename MMC_MODE_ to DRVR_CAP.
* Move quirks into ctrlr->caps.
* Associate removeable with the controller.
* Statically allocate MmcMedia.
* Replace the SdhciHost structure with the MmcCtrlr structure.
* Split the code to support other SD/MMC controllers.
* Split out erase and write support.
* Update the code to be more consistent with the coreboot coding style.
* Only expose calling APIs.
* Divide up mmc.c into 4 modules: MMC, SD, storage card, common code.
* Update debug and error messages.
* Add partition support.
* Display clock frequencies once in MHz.
* Remove mmc_send_cmd, use ctrlr->send_cmd instead.
* Handle error from sd_send_op_cond.
* Allow mainboard to control delays around CMD 0.
* Support command logging.
* Mainboard may set delay after SD/MMC command.
* Display serial number with sd_mmc_trace.
* Remove cmd set parameter from mmc_switch.
* Display errors for timeout and comm errors.
* Add LED support.
* Move 64bit DMA flag into ctrlr->caps.
* Rework PIO transfer routine.
* Add HS200 bus tuning.
* Add support for HS400.
* Use same format for HS400, HS200 and HS52.
* Reduce storage_media structure size
* Add routine to update code pointers
* Add display of storage setup
* Display controller setup
TEST=Build and run on Reef and Galileo Gen2
Change-Id: I2666347879066a8920494feced97e6bb7218d757
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eef40eb2a9
Original-Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19208
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/486775
Add a Kconfig value to indicate coreboot builds.
Add prototypes and definitions for:
* dma_coherent
* dma_malloc
* xmalloc
* xzmalloc
Move prototype for memset into stdlib.h from string.h to eliminate build
breaks.
TEST=Build and test on Galileo Gen2
Change-Id: I43d69466a55f18f179b56bd9cd9d5ff8ea058ad8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb70c40f2e
Original-Change-Id: Ib2eb2ca143b0538bdd1863e628af4c1948bc0f8c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19207
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/486774
For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3c561f2bcffeb7e76159c529049c7aaeb7143a13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00fd3ff507
Original-Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19337
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486761
There is no need to override CBFS_SIZE since there is no additional
firmware needed on the flash.
Also due to it having a description CBFS_SIZE was displayed twice in
menuconfig, which is fixed by this.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14d3948338e1cf4b644bcd915f21d7a62ef13730
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e1194567f
Original-Change-Id: I1a8e2e458ac4d420f3fd4628c2805b6d4e2ee529
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19331
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/486760
Tested on X230 with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.
This is a copy-paste of I8e02c8003ff745d05ee272c59377174847f5219c.
BUG=none
BRANCH=none
TEST=none
Change-Id: If193f6fa4d997e04d8b18a602dd5904e6c6abbfc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 166eaca9d8
Original-Change-Id: I8f270d558668c1fe41bcdcc7d6d2aa7f053c85b6
Original-Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19412
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486759
Lid switch is not available.
Hence report lid state as always open.
BUG=none
BRANCH=none
TEST=none
Change-Id: I64d1c491e583bbdc3e48e1d87b39eb2043b3e71e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3a117908c
Original-Change-Id: Ia9c82c3ad323912bad51cf55ed80a37b3110b1ef
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19219
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/486758
Use spi_setup_slave to fill up the spi_slave structure with
pointer to spi_ctrlr structure which can then be used to perform all
spi operations.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5b6a8bdfdb2340abdebe17cfcc52346f7fcb7f9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e49b0a2c5
Original-Change-Id: I2804ed1e85402426a654352e1ceaf0993546cd8b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19385
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/486755
Depend on I2C_TPM to prevent showing the menu entry on systems
that do not have an I2C TPM installed.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idb9e04bb8e16bcba294403cd718eecb2504547ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d74836488
Original-Change-Id: I7cd647c9c7e9721eab96ab64b844a882f156ee68
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19374
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/486753
Read DRAM SPD and populate MemorySpdPtr fields
in UPD data structure for FSP.
BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
We are currently working on bringup and have no
hardware to test on yet.
Change-Id: I668d51f613176b5d46b71830c169c317abc4b1d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 031c818633
Original-Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19205
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486750
This board was added while the latest libgfxinit changes were in review.
Update to make it compile again and sanitize the port list.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia0cfaad77bdda3b09771a4d7184f1fdb0f58f4af
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7f28700f4
Original-Change-Id: I81b96e225945a8f8e47b64cefea91eb2747675ca
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19353
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://chromium-review.googlesource.com/486749
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ied3d7e52f9a905e10b07a65b501e7ba5e0a950fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b4d2cfc73
Original-Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19291
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486748
MMA blobs internal version 2.1018 adds more tests.
This patch updates the script to accommodate that
change. MMA blobs are part of chrome private
repository.
BUG=none
BRANCH=none
TEST=none
Change-Id: I66ea2a64c0ef268cd624909413123dc06a0d06ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0bb611d125
Original-Change-Id: Iff660fdfdfcd7acc3820c5550740276be6213877
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19259
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486747
Use the iobuf API instead of relying on own buffer management. It
also provides consistency between marshaling and unmarshaling code
paths for propagating return values instead of overloading the values
of existing variables.
BUG=b:36598499
Change-Id: I8506c943385242ce91f72e2d2d61ad931eb0e221
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee049fa802
Original-Change-Id: Iec0bbff1312e8e6ec616d1528db8667f32e682c9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19063
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/486745
Introduce ibuf and obuf structures for helping manage memory buffers.
The ibuf, an input buffer, can be read from and the obuf, an output
buffer, can be written to. Helper functions are provided for serializing
values in different endian formats. This library is provided to for
common buffer management routines such that the same code doesn't
have to re-written in different and less consistent forms.
BUG=b:36598499
Change-Id: I9856477b54d636504443e278850de42e9a199ac6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88b26b845c
Original-Change-Id: I5247237f68b658906ec6916bbbb286d57d6df5ee
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19062
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/486744
- Refactor the spec & setter file reads into a separate function.
- Make sure files can actually be opened before reading from them.
- Check all malloced variables.
- Set functions with no declatations as static.
- Update blobtool.tab.c_shipped to the latest version.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idd95683db15a82debb705f1b722ac94fcb57ee8e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6338189d0e
Original-Change-Id: Ie97fff84493a06f48d8673d388c3882028d048ca
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19231
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/486743
- Rewrite STRING and COMMENT expressions to remove need for CHARS.
- Clean up regular expressions - get rid of unnecessary expressions.
- Remove extra newline from the end of the file.
- Clean up stripquotes() function
-- Remove unnecessary backslashes in '\"'
-- Check malloc for failure
-- Remove unnecessary assignment of 0 to the end of the new string,
snprintf will take care of it.
- Update blobtool.lex.c_shipped to the new version.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57e90fbbd56ad24c36e3a4ea1b4ffb05bc6fd5ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6d189cc47b
Original-Change-Id: I002962cfae0816ed3c7a5811dfb1b8b48fdc5729
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19230
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/486742
The function decode_spd uses undeclared variables and an incorrectly
initialized array.
BUG=none
BRANCH=none
TEST=none
Change-Id: I896b374368ecc4e217297402ac98d93a059bf4c3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 097d753980
Original-Change-Id: Ib45a8b2946c04c270e29524675b1f09d491d282b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19336
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/486741
In the single GPU configuration, the T420 has an LVDS port, one DP++
and one VGA port connected to the IGD. Docking solutions feature up to
two additional DP/DVI-D ports, also directly connected to the IGD.
This makes the list of ports to probe pretty long (takes about 70ms
if nothing but LVDS is connected). We could save about 20~30ms if we'd
limit the ports in case we are not docked or have a discrete GPU.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0962250265865c84a3a61aaa52e3c0681bdb9bdc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8795feb644
Original-Change-Id: I8e02c8003ff745d05ee272c59377174847f5219c
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19378
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/486740
This commit changes the interrupt configuration for the touchpad to be
level triggered so it matches what the device is actually using.
When the system wakes from suspend by way of touchpad interrupt, or
there is touchpad input while in suspend that does not wake the device
(when the device is in tablet mode) the interrupt edge is not seen by
the AP so the driver does not handle the event and the touchpad keeps
the interrupt asserted and does not send further interrupts. The end
result is a non-functional touchpad after resume until it is reset or
the driver is reloaded.
This happens because the touchpad is actually treating the interrupt as
level triggered and expects the kernel driver to read a data packet over
I2C before it will de-assert the pending interrupt.
BUG=b:35774857
BRANCH=none
TEST=Test that the system can reliably wake from suspend by touchpad
event via the EC and continue to have a functional touchpad after resume.
Change-Id: I96e049744416f0e5ac10568be23992945d190723
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b86ccbbeab
Original-Change-Id: Iaf7c04d9bc9d945bdcc196dff54c92a2a68368f3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19382
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486739
Unlike other oak derivatives, Rowan uses an 8-lane BOE tv097qxm-nu0
MIPI/DSI panel that requires dual DSI support.
Rework oak display initialization to special case Rowan, which uses a
provided edid struct for its panel, special panel backlight sequencing
and needs to configure mtk_ddp and mtk_dsi to use dual dsi mode.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel
Change-Id: I136ba5bd1ab12c4ad92995e066fc6d6cf54d0898
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19389
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482745
The MT817x display output pipeline can be configured to drive an 8-lane
MIPI/DSI panel using "dual DSI" mode. For the "dual DSI" video data path,
the UFO block is configured to reorder the data stream into left and right
halves which are then sent by the SPLIT1 block to the DSI0 and DSI1
respectively. The DSI0 and DSI1 outputs are then synchronously clocked at
half the nominal data rate by their respective MIPI_TX0/MIPI_TX1 phys.
Also, update the call sites in oak mainboard to avoid build breakage.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel
Change-Id: Id47dfd7d9e98689b54398fc8d9142336b41dc29f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19361
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439027
This helper function was introduced so that mainboards don't need
to manually fill in these struct edid fields.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel
Change-Id: Ic9404a786a28b314b710e037dcae776be4b584ca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19388
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482744
This patch enables TPM2 using cr50 over I2C for the Rowan board, and
adds an mt8173 specific TPM IRQ polling function. The function relies on
the appropriate EINT input configured to trigger the ready status on
the rising edge.
The cr50 TPM is on I2C address 0x50.
The cr50 interrupt GPIO is also made available for use by depthcharge
via the coreboot tables.
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19364
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/442306
Add basic support to configure GPIOs to poll for external interrupts
(EINT).
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: I9d52591661a5a74ec1fd9a081f606f0a08a3a6ab
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19362
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/479497
The vendor.irq field was originally intended for use as the TPM 1.2
"command complete" interrupt. However, all actual coreboot tpm drivers
and hardware use the vendor.status method of checking command completion
instead, and this irq field is not used.
Let's just remove this unused functionality to simplify the code.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I994c5bfbd18124af9cb81d9684117af766ab0124
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19396
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/484120
DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies
the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM".
Change-Id: If66a2a1d461a411e112589c84a434066d48b9399
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19410
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/486484
DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies
the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine.
BRANCH=none
BUG=b:36786804
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM".
Change-Id: Ia1eacd15e71a46a37457ee2f117b156393c3393d
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19409
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/486483
The Cr50 TPM uses an IRQ to provide a "status" signal used for hand-shaking
the reception of commands. Real IRQs are not supported in firmware,
however firmware can still poll interrupt status registers for the same
effect.
Commit 94cc485338 ("drivers/i2c/tpm/cr50: Support interrupts for status")
added support for the Cr50 driver on X86 platforms to use a KConfig file
to supply an IRQ which it would poll using acpi_get_gpe. If the IRQ is
not supplied, the Cr50 driver inserts a 20 ms wait.
Unfortunately this doesn't work so well when using the i2c connected Cr50
on ARM platforms. Luckily, a more generic implementation to allow a
mainboard to supply a Cr50 IRQ status polling function was solved for SPI
connected Cr50s by commit 19e3d335bd ("drivers/spi/tpm: using tpm irq to
sync tpm transaction").
Let's refactor the i2c c50 driver to use this same approach, and change
eve and reef boards to make use of DRIVER_TPM_TIS_ACPI_INTERRUPT for
specifying the TPM flow control interrupt.
This essentially reverts these two commits:
48f708d199 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe
94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status
And ports this commit to i2c/tpm/cr50:
19e3d335bd drivers/spi/tpm: using tpm irq to sync tpm transaction
As a side effect the tpm_vendor_specific IRQ field goes back to its
original usage as the "TPM 1.2 command complete" interrupt, instead of
being repurposed to hold the flow control IRQ.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I004329eae1d8aabda51c46b8504bf210484782b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19363
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/440871
Utilize the intel/common code for tis_plat_irq_status() to remove
dependencies and code duplication on for bringing up a board
requiring tis_plat_irq_status().
Change-Id: I2aaa1d7d3ce171dc1788438ff9990fce533deb6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19371
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/482743
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
On Intel platforms utilizing the CR50 TPM the interrupts are routed
to GPIOs connected to the GPE blocks. Therefore, provide a common
implementation for tis_plat_irq_status() to reduce code duplication.
This code could be further extended to not be added based on
MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now.
Change-Id: I955df0a536408b2ccd07146893337c53799e243f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19369
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/482742
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
The CR50 TPM can do both SPI and I2C communication. However,
there's situations where policy needs to be applied for CR50
generically regardless of the I/O transport. Therefore add
MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally,
once the mainboard has selected CR50 TPM automatically select
MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0.
Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19370
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/482741
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
MAINBOARD_HAS_SPI_TPM_CR50 describes a capability of the board and SPI_TPM
is only on if we actually want to compile in the TPM code. For example,
in src/drivers/i2c/tpm/Kconfig MAINBOARD_HAS_I2C_TPM_CR50 also doesn't
depend on SPI_TPM.
This problem manifests itself as the following build issue when building
with MAINBOARD_HAS_I2C_TPM_CR50 but without an explict "select TPM2":
src/Kconfig:296:error: recursive dependency detected!
src/Kconfig:296: symbol MAINBOARD_HAS_TPM2 is selected by MAINBOARD_HAS_TPM_CR50
src/Kconfig:408: symbol MAINBOARD_HAS_TPM_CR50 depends on MAINBOARD_HAS_SPI_TPM_CR50
src/drivers/spi/tpm/Kconfig:15: symbol MAINBOARD_HAS_SPI_TPM_CR50 depends on SPI_TPM
src/drivers/spi/tpm/Kconfig:1: symbol SPI_TPM depends on TPM2
src/Kconfig:396: symbol TPM2 is selected by MAINBOARD_HAS_TPM2
MAINBOARD_HAS_SPI_TPM_CR50 shouldn't depend on SPI_TPM.
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: I0cb3f6d3aa4159bad563a6a4b006d7f4825e04b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Suggested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19411
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486480
This patch allows the CBMEM console to persist across reboots, which
should greatly help post factum debugging of issues involving multiple
reboots. In order to prevent the console from filling up, it will
instead operate as a ring buffer that continues to evict the oldest
lines once full. (This means that if even a single boot doesn't fit into
the buffer, we will now drop the oldest lines whereas previous code
would've dropped the newest lines instead.)
The console control structure is modified in a sorta
backwards-compatible way, so that new readers can continue to work with
old console buffers and vice versa. When an old reader reads a new
buffer that has already once overflowed (i.e. is operating in true ring
buffer mode) it will print lines out of order, but it will at least
still print out the whole console content and not do any illegal memory
accesses (assuming it correctly implemented cursor overflow as it was
already possible before this patch).
BUG=chromium:651966
TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco.
Also confirmed correct behavior across suspend/resume for the latter.
Change-Id: I927df6bbffa13fdce9d1984278afa340042f7ac9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d67c6876b5
Original-Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18301
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482975
Issue TPM startup on romstage completion via common LPC TPM
code if the TPM was enabled in Kconfig.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9bfddcc809d99f8cc3913e1a2d60f6358e21d1f2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2d35809530
Original-Change-Id: Id886d6aeefa045fb979f128b1cf4c10fff243b24
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/19338
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482974
Move include of reg_access.h from pci_devs.h to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: I0bd92d9594315278449ea9241c951a58e4ff44d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0a60383b2
Original-Change-Id: I0d2de96f51c56001cdd06c7974cbc649fde1e89c
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19355
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/482973
