Hide the detail of allocation from cbmem from the FSP.
Loading of a BMP logo file from CBFS is not tied to FSP
version and we do not need two copies of the code, move
it under lib/.
Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We can never pass memory location of dynamically loaded BMP files in the
static devicetree. The parameters passed to FSP are filled at runtime.
Change-Id: Ib835ec0d9349ec96d5635e228063f2b7000b70fd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The only reference to CID1 is in common/acpi/wifi.asl and
only two braswell boards include it. Everywhere else
the value in GNVS was unused.
Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix compilation on GCC 10.2.1 and address the underlying issue. The
printf format specifier for a size_t type is z.
Change-Id: Ieb1db6c0c3eb4947bd3617e418bac238b70ec08f
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Alderlake includes latest VBT (version 237 onwards),which has size of
8.5 KiB. This change is specific to alderlake so utilizing Kconfig option
to increase VBT size specifically for ADL platforms.
BUG=None
BRANCH=None
TEST=Include new VBT and boot the platform. Able to see firmware screen
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.
This implementation also selects the respective MP services PPI version
supported for SoCs
BUG=b:169196864
Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE.
FSP_PEIM_TO_PEIM_INTERFACE is used for:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
* Adding ppi to subdirs-y
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
and is selected by SoCs that want to enable MP PPI services.
Instead of using the indirect path of selecting MP PPI services, this
change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The
above uses are handled as follows:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
--> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI.
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
--> The guard isn't really required. The Kconfig options in this
file don't present user prompts and don't really need to be guarded.
* Adding ppi to subdirs-y
--> Makefile under ppi/ already has conditional inclusion of files
and does not require a top-level conditional.
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
--> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC.
TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom
Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was commented that the need for the delay was mainly related
to external displays and only with VBIOS execution. Move the
delay such that it is done only when we actually need to execute
the VBIOS aka option rom.
A delay is currently only defined for librem/purism_bdw in
its Kconfig. As the description of the issue sounds like it
would equally happen on other platforms when VBIOS is involved,
promote the Kconfig visible option to global scope.
Change-Id: I4503158576f35057373f003586bbf76af4d59b3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.
They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.
It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.
Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.
Tested=Execute "dmidecode -t 4" to check max speed is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This is what Lynxpoint does. It is equivalent, but simpler.
Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47045
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Crash Data are collected and sent to the OS via the ACPI BERT.
BUG=None
TEST=Built, and BERT successfully generated in the crashLog flow.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df
Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.
BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level
Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Because ACM already does TPM initialization.
Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Baytrail had (only) occurence of DwordMemory vs DWordMemory.
Braswell one had bogus comments about the PCI memory range.
The actual region details are dynamically filled in _CRS.
Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).
ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).
Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UPD PlatformDebugConsent field is not configured.
The config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT is available but not
used. Use this config value for PlatformDebugConsent.
BUG= N/A
TEST= Build Intel Elkhart Lake
Change-Id: I697fb611dfb23e107fa8ef1543424b9797a7d027
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50108
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add device ID of Cannon Lake PCH-H Mobile HALO SATA controller
in supported device table.
Bug=N/A
TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully
completed
Change-Id: Ie1c2aa8273a53c47d7b3571394bcd85b59ab1142
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Bus Master is not required and reference code does not set it.
Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Get rid of custom microcode caching in MPinit and SGX code and
use the caching introduced in intel_microcode_find() instead.
Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This cleans up the postcar frame setup, which now gets used instead of
just going with TempRamExit MTRR's.
Note that ramstage CPU init sets up different final MTRRs anyway.
TESTED on ocp/deltalake and ocp/tiogapass.
Change-Id: I756c2d479fef859a460696300422f08013a300f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Allow platforms to use the coreboot postcar code instead of calling
into FSP-M TempRamExit API.
There are several reasons to do this:
- Tearing down CAR is easy.
- Allows having control over MTRR's and caching in general.
- The MTRR's set up in postcar be it by coreboot or FSP-M are
overwritten later on during CPU init so it does not matter.
- Avoids having to find a CBFS file before cbmem is up (this
causes problems with cbfs_mcache)
Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before enabling IO decode ranges, current code checks if the DMI SRLOCK
is set to prevent inconsistencies between LPC PCI cfg registers and LPC
DMI registers, when the latter are locked.
DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H,
PCH-S and others with discrete PCH packages. So this check is at least
incomplete.
Further, the lock gets applied by FSP and gets reset on a warm reset.
Thus, there is no case where the lock would be already set at the
places where the DMI registers get written currently.
Drop the checks for the reasons mentioned above.
Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to die here. Also simplifies merging with Haswell.
Change-Id: I3d4bc79b32279180442dbc82126e297f11f1fb80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The remaining code in this file is PCH-specific.
Change-Id: I0e4924e680db9c25aeb222bdd478b3282a77b34f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49946
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This small function is only used in one place.
Change-Id: Ieccdca60fb7837b6406a6b2fd7ebae86958a1afe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
