We use mmu_ranges to track the list of memory ranges and their types for
MMU initialization. We also keep track of used memory ranges in
usedmem_ranges, to avoid them from being re-allocated in
mmu_alloc_range().
The problem is, the CBMEM range (CB_MEM_TABLE) is added to mmu_ranges,
but is never marked as "used" in usedmem_ranges. This potentially causes
any allocation (for example the framebuffer) to overlap with CBMEM. This
issue is observed when DMA_DEFAULT_SIZE is reduced from 32MB to 1MB [1].
Prior to that change, because there isn't enough space above the
coreboot table (with the 4GB upper limit) to fit the 32MB requested
region, the DMA heap is always allocated *below* the coreboot table. And
because the coreboot table is usually the lowest within CBMEM, the DMA
heap region is allocated *below* the whole CBMEM, which happens the
avoid the issue.
Fix the bug by adding CB_MEM_TABLE ranges to usedmem_ranges. The ranges
in usedmem_ranges don't need to be combined because they are not for MMU
initialization (and there's only one CB_MEM_TABLE range).
[1] commit aedc177f00 ("libpayload: arm64: Reduce DMA allocator space to 1MB")
BUG=b:424107889
TEST=emerge-skywalker libpayload
BRANCH=none
Change-Id: Ie9ecafc17546e524253c60ab684ec10ff3495998
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This reverts commit aedc177f00.
Reason for revert: With this change depthchange clears parts of cbmem on Google/Corsola when display is cleared.
BUG=b:424107889
Change-Id: I6cc21693ddcaed59e41e333b773e0baeb29d3b40
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88051
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
I got 'nm' usage error when i built coreinfo payload.
nm: unrecognized option '--no-weak'
it seems that this is occurred by using nm for host, not for coreboot.
So, I replace nm with $(NM)
Change-Id: I0a0a04b351c9131b1238e8cc7e63e396820494d9
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Unit tests should always use a mock ndelay() defined within each test.
Therefore, select ARCH_HAS_NDELAY for ARCH_MOCK.
Change-Id: I2680e37034d4d13058b3e778d72e63fc6ed18313
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Weak symbols don't work as expected when you try to override them from
within the same static library. Static libraries are just archives of
individual objects, and when the linker tries to resolve a symbol
against it it simply uses the implementation from the first object that
has one, weak or not. It does not search through all remaining objects
to see if there's also a strong implementation.
We've had multiple cases in libpayload where builds were incorrectly
using the default implementation rather than an optimized arch-specific
implementation for years due to this issue. To prevent it from
recurring, this patch adds some postprocessing script to the Makefile
that checks for this situation and makes the build fail if it creeps in
again.
Change-Id: I9fcbc9b873901d126322b12954c349c08300369f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On arm64 device libpayload reserves 32MB of space for the DMA allocator.
DMA allocators are usually just used for small bounce buffers or DMA
descriptors for SPI, I2C or USB transfers, nothing that should get
anywhere near the size of megabytes.
Presumably the original number was just made arbitrarily large because
it didn't matter. But more recently we have had security applications
(guarding secrets that get received over SPI/I2C from firmware and must
not be visible to the OS after handoff) that made us want to erase the
entire DMA heap just to be sure no driver left a copy of any secret
lying around there. This means the size is no longer fully harmless
because erasing a larger heap takes more time.
Change the default to 1MB which should still be more than more than
enough for any real applications, but should bring the time required to
erase it back into negligible territory.
BUG=b:418942992
TEST=Booted Trogdor from USB.
Change-Id: Id56486203c512d7ff08909cac1a016adc44d8e68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Weak symbols don't work as expected when you want to override them from
within the same static library. This patch changes the arch_ndelay()
function so that instead of having a weak generic implementation, the
choice between generic implementation and an arch-specific override is
explicitly made by Kconfig. Let's also drop the "arch_" prefix and just
call this ndelay().
Change-Id: Ie4fe2734e0683fa3537e2ebcabfe067e7499463a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87776
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Our mechanism to override the default (pure C) memory function
implementations (memset, memcpy, memmove) with architecture-specific
optimized assembly versions doesn't actually work: it turns out that
weak functions don't work as you'd naively expect when you pack them
together with a strong definition from a different object into a static
library. When a linker tries to resolve a symbol from a static library,
it just picks the first one it finds, even if it is weak. It doesn't
evaluate all objects in the library to see if there are other strong
definitions.
To fix this, this patch gets rid of the weak symbols and uses Kconfigs
instead. It adds an optimized memmove() implementation for x86 because
that makes things easier (then all architectures either override all
three functions or none of them). Also remove memcmp() from the
functions that can be overridden for now because nobody ever needed that
anyway.
Change-Id: Iedf9898247f1999e56fde3233fad8b7cb36b1269
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87766
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing lanczos_weight() implementation naively follows the purely
mathematical definition for the `x == 0` special case. However, the
point of defining that special case is obviously to prevent division by
zero in the general case formula. Unfortunately we are still doing some
multiplications with `x` before we get to the division step, and our
fpmath library loses precision during multiplication. This can lead to
edge cases where `x` is not zero but `x_times_pi` later ends up being 0,
which causes the division to throw an exception after all. (I guess
we've just been lucky to not see this case in practice for now... it
requires the output pixel coordinate to be extremely close to but not
quite on the next input pixel coordinate, which may be rare in practice
with our scaling algorithms.)
This patch fixes the issue by implementing the special case later and
checking if `x_times_pi` is zero instead. Note that as long as we pass
this check, we can be confident that the division cannot fail even
though fpdiv() also truncates the divisor: this is because `x_times_pi`
was calculated from an fpmul() call with the constant fppi(), which has
34 significant bits. Even if x is the smallest possible non-zero value
after scaling for multiplication, the result `x_times_pi` must still
have 18 significant bits. That means it can be scaled down a further 16
bits for division without becoming zero.
Also add a simple unit test forcing exactly this condition to ensure the
code will not regress.
Change-Id: I2f212ee5df38252e97ec55aba3d2d25320c4b102
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Disks larger than 2TB (technically disks with more than 2^32 blocks, but
for the common block size of 512 that comes out to 2TB) cannot represent
their full amount of blocks in the SCSI READ_CAPACITY(10) command used
by libpayload's USB mass storage driver. The entire driver isn't written
to support block addresses larger than 32 bits anyway.
The SCSI command has been designed in a clever way so that devices are
supposed to return the maximum value (0xffffffff) if the actual value
doesn't fit. However, our code adds one to the value (because it is
actually the address of the last block, but we want to know the number
of blocks). This makes it overflow back to 0 which is not great.
This patch caps the result before incrementing it so that the overflow
cannot occur, allowing us to at least access the first 2TB of super
large USB sticks.
Change-Id: Ic445923b7d588c4f523c4ed95a06291bc1969261
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add an allocation of an empty buffer for the Android protected virtual
machine firmware within cbmem. The buffer will be filled by the payload
and the purpose is to just reserve the memory. cbmem is used to make
sure that the region won't overlap with other reserved regions
or device regions.
BUG=b:354045389
BUG=b:359340876
TEST=depthcharge receives the buffer through lib_sysinfo
BRANCH=main
Change-Id: I48efc033ac0f5fbfcf3a52fabf40be016cd4c6f7
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
libpayload stdint.h only supports typedefs for datatypes of exact
bits. This makes libpayload less flexible to support libraries
that reference different data types.
Add fast data types in types.h.
BUG=b:386913035
Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74
Signed-off-by: Masa Nakura <nakura@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86632
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry.
It is annoying when searching for the wrong abbreviation in the spec so
fix it everywhere it occurs.
source: Intel 64 spec April 2022 and AMD64 spec April 2024.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I730235beea69b3720f080bbade083c2eeed26587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
selfboot() doesn't really need to be architecture dependent. All
architectures are essentially doing the same thing with a normal
function call, only x86_32 needs an extra attribute. arm64 and x86 also
previously haven't been passing the coreboot table pointer, even though
they should. This patch fixes that.
Change-Id: If14040e38d968b5eea31cd6cd25efb1845a7b081
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86142
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new config to libpayload whose sole purpose it is to
be as different as possible from the defconfig, in order to try to get
the CI to exercise more code paths and thus catch more issues.
Change-Id: Ia6bd7572056b7a02acb686542810e661e015cc69
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The mock/arch/cache.h file exists for libpayload unit tests. However,
the default implementations (as empty macros) in it make these functions
difficult to mock in unit tests.
Therefore, we follow what's done for mock/arch/io.h, by only including
function declarations in the header. Each test is expected to implement
mocks for these cache functions when required.
Change-Id: Ie4383bf95435fd7d74d624b19b79b5a117cf6d00
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
This makes it easy to switch between x86_32 and x86_64 in payloads.
Change-Id: I3ac5f24d83dc80db924e92b53403c477e6256c44
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The value used is not acceptable to BFD linker.
Change-Id: I0f134a96c596d69e10dd441b96184b119e9f1908
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84013
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows nvramcui to be build with clang.
Change-Id: I5e56ead81fc92b7ba4fb63a2c098b0e10b01ca53
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84010
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commonlib/region.h requires SIZE_MAX to be defined.
Change-Id: I588d59c2637b10def046ea02293e5503c9b6bc3d
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83907
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add strlen() and strnlen() to commonlib/bsd by rewriting them from
scratch, and remove the same functions from coreboot and libpayload.
Note that in the existing libpayload implementation, these functions
return 0 for NULL strings. Given that POSIX doesn't require the NULL
check and that other major libc implementations (e.g. glibc [1]) don't
seem to do that, the new functions also don't perform the NULL check.
[1] https://github.com/bminor/glibc/blob/master/sysdeps/i386/strlen.c
Change-Id: I1203ec9affabe493bd14b46662d212b08240cced
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83830
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change removes the unnecessary conditional compilation around
CBMEM_ID_CSE_BP_INFO and CBMEM_ID_CSE_INFO handling in
cb_parse_cbmem_entry. These CBMEM IDs are only relevant on platforms
with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD enabled, and platforms without
this config option won't encounter these IDs when calling
cb_parse_cbmem_entry().
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch adds support for x86-64 to the rdtsc() function, allowing
it to correctly read the Time Stamp Counter (TSC) on both 32-bit and
64-bit x86 architectures.
BUG=b:242829490, b:351851626
TEST=Builds and boots on google/rex0 and google/rex64 systems and
manually verified correct TSC readings on x86-32 and x86-64 hardware.
Change-Id: I0afac3db2e82a245a37c2e5cf2302bf1dad62c01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch refactors the handling of CSE CBMEM IDs to enable platforms
to choose whether to perform CSE sync operations within coreboot or
defer it to the payload. This separation improves code organization,
ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks.
Now, platforms can select:
* `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot
* `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync
This change ensures mutually exclusive options, avoiding unnecessary
SPI flash size increases.
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 64 bit encode/decode functions to libpayload, since it is required
in the patch that moves device_tree to commonlib.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5dba9a7f41147a511ba1250786e7c51ce623e70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83082
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set a pointer in lib_sysinfo for CSE_BP_INFO and CSE_INFO.
BUG=b:343022317
TEST=Verified CBMEM data in depthcharge on Screebo
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I3aa64d1e439a0596e732a3c0608d60913cefd19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Removed an extra space character from the `printf` format string in
`dump_exception_state` to ensure proper alignment of register values
when printed during exception handling.
BUG=b:336265399
TEST=Built and booted google/rex64 successfully.
Verified correct alignment in exception state dumps.
Change-Id: I8ff92775e32ee754967b1b0a43cd68971b4aadfc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83047
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field
description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented.
If numsets and associativity from CCSIDR_EL1 are not correct, the system
would hang during mmu_disable().
Rather than assuming that FEAT_CCIDX is not implemented, this patch
adds a check to dcache_apply_all to use the right register format.
Reference:
- https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770
BUG=b:317015456
TEST=mmu_disable works on the FEAT_CCIDX supported SoC.
Change-Id: I892009890f6ae889e87c877ffffd76a33d1dc789
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82636
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
- Added `$(obj)/libpayload-config.h` as a dependency for the `lib`
target.
- This ensures the config header is up-to-date before building the
library.
TEST=Able to build google/rex.
Change-Id: If26336f6261aadf611fa5338c4300873156cc3da
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch introduces x86_64 (64-bit) support to the payload, building
upon the existing x86 (32-bit) architecture. Files necessary for 64-bit
compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig
option.
BUG=b:242829490
TEST=Able to verify all valid combinations between coreboot and
payload with this patch.
Payload Entry Point Behavior with below code.
+----------------+--------------------+----------------------------+
| LP_ARCH_X86_64 | Payload Entry Mode | Description |
+----------------+--------------------+----------------------------+
| No | 32-bit | Direct protected mode init |
+----------------+--------------------+----------------------------+
| Yes | 32-bit | Protected to long mode |
+----------------+--------------------+----------------------------+
| Yes | 64-bit | Long mode initialization |
+----------------+--------------------+----------------------------+
Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Integrate head.S directly into libc and remove all instances of head.o.
* Drop 'separate class' entry for head.S.
* Drop special treament for head.o inside lpgcc.
* Change the .text in `x86/head.S` to `.section .text._entry`.
* Drop arch/mock/head.c, initially added as a dummy file.
Change-Id: I156d781908fcc38d455bbf9f2c29e5ab95c7775a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This moves the multiboot header into its own include file, simplifying
head.S and making it easier to include/exclude the multiboot header
based on config options.
BUG=b:242829490
TEST=Able to build and boot google/rex.
Change-Id: I59a22dfe36044b4dd64a5b028a134be7a7d02a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit renames the variable _ARCH to _ARCHDIR in the libpayload
build script (lpgcc) to align with the naming convention of other
variables used in this file.
This change improves code readability and maintainability.
Change-Id: Iea4af68e49ab1cd7ec8156a14f8215244e9c0622
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82479
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CONFIG_LP_MULTIBOOT is enabled, save the values of EAX and EBX
passed from the bootloader. This information can be useful for
multiboot payloads feature alone.
Change-Id: I98c2cd00206ee48eb0fc67edd9533032bcf3e5eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82040
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Change `inl()` return type from `unsigned long` to `unsigned int` to
match the function definition and ensure consistency across platforms.
BUG=b:242829490
TEST=Compiled successfully in 32-bit and 64-bit modes.
Change-Id: I681935665c8de9ee472ab72fe1ac2f5dcc0f2534
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This patch makes the GPL-restricted commonlib helpers available in
libpayload when CONFIG_LP_GPL is selected, as a convenience to GPL
payloads that use them a lot.
Cq-Depend: chromium:5375721
Change-Id: I844c6e700c4c0d557f97da94fa3aa2e868edd756
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
