CPUID 0xf47 tested on on 945G-M4 board.
Needs more MSR's consistency tests.
To do: test if speedstep.c and speedstep/acpi.c
are ok for model_f4x.
Change-Id: I285ad33804592e3df510d61dd24f14f944e05142
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/17409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Platforms moved to POSTCAR_STAGE so these are no longer used.
Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These chips are still using LATE_CBMEM which was agreed upon to
be removed after release 4.7. It is now more than 1 year later
and they still linger around.
The work and review to bring this code up to date can happen on
the 4.9 branch and then squashed together and merged back into
mainline when done.
Change-Id: I11290a5e92397b9b7e7e5a19b029278e728671a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Newer CPUs/SoCs need to configure other features via the
IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the
msr is already locked. Create separate functions for setting the
vmx flag and lock bit, and rename existing function to indicate that
the lock bit will be set in addition to vmx flag (per Kconfig).
This will allow Skylake/Kabylake (and others?) to use the common
VMX code without breaking SGX, while ensuring no change in functionality
to existing platforms which current set both together.
Test: build/boot each affected platform, ensure no change in functionality
Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30229
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function returns APIC id for respective cpu core.
BUG=b:74436746
BRANCH=none
TEST=mp_get_apic_id() can be accessed in other files now.
Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/25620
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All i82801gx targets now use SMM_TSEG.
Change-Id: Ib4e6974088a685290ed1dddf5228a99918744124
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel DG41WV, resume from S3 still works fine.
Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common SMM_TSEG code to relocate the smihandler to TSEG.
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel d945gclf and Lenovo Thinkpad X60.
Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I00d15d0640a37f89ffd5cc87b89d5ba11fecb9ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29887
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29886
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
POWER8 is a specific implementation of ppc64, which is by now outdated
(POWER9 has been on the market for a while). Rename arch/power8/ to
potentially cover a wider range of hardware.
TEST=Toolchains built before/after this commit can build coreboot for
emulation/qemu-power8 from before/after this commit.
Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
No need to hide prompts, it's a user choice anyway, they should know.
The help texts were just rephrasing the prompts or stating the obvious.
Change-Id: I5694a88f2da57af2a20357c4e22c7c648053cc26
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29802
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Gather x86 specific debug options and deflate their code a little. We
keep their hiding rules and help texts, although they don't seem much
useful.
Change-Id: I3bb8e759fc6a4871d30fccff47babfb7a291b45c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29751
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow
backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART,
because it's using its interface. The individual UART drivers
select DRIVERS_UART, because they implement the interface and
depend on the common UART code.
Some guards had to be fixed (using CONSOLE_SERIAL now instead of
DRIVERS_UART). Some other guards that were only about compilation
of units were removed. We want to build test as much as possible,
right?
Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's a typo in the cpu driver causing it to always use the weak
implementation defined in the devicetree instead of the real
implementation.
Tested on qemu-q35, the CPU driver contains valid values.
Change-Id: I4a6bb447bfdb3df6053c0df8be9d7c6aa8f689be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/29675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like
VBOOT with separate verstage.
Changes:
* Use symbols to set up CAR and STACK
* Zero CAR area
* Move BIST failure checking to cpu folder
* Rename functions where necessary
Tested:
* qemu-2.11.2 machine pc
* qemu-2.11.2 machine q35
Test result:
* BIST error reporting is still working.
* Console starts in bootblock
* SeaBios 1.11.2 as payload is still working
Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow
ramp rate during `initialize_vr_config()` results in the following
exception, causing the system to hang.
CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
Code: 0 eflags: 00010006 cr2: 00000000
eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90
So, only change this setting for Haswell ULT CPUs, as suggested by the
BIOS Writer's guide.
Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.
CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
Code: 0 eflags: 00010006 cr2: 00000000
eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90
The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR only exists on Haswell-ULT CPUs.
So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.
Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
