coreboot/src/cpu
Tristan Corrick ba8ead817d cpu/intel/haswell: Allow use of TSC for the monotonic timer
When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.

	CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
	Code: 0 eflags: 00010006 cr2: 00000000
	eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
	edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR only exists on Haswell-ULT CPUs.

So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.

Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 22:22:57 +00:00
..
allwinner Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
amd reset: Finalize move to new API 2018-10-31 15:29:42 +00:00
armltd vboot2: add verstage 2015-01-27 01:41:40 +01:00
intel cpu/intel/haswell: Allow use of TSC for the monotonic timer 2018-11-01 22:22:57 +00:00
qemu-power8 Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
qemu-x86 qemu-q35: Use the TSC for udelay 2018-09-06 16:31:10 +00:00
ti src: Add missing include <stdint.h> 2018-11-01 11:25:07 +00:00
via src: Remove unneeded whitespace 2018-10-23 15:52:09 +00:00
x86 x86/mp_init: Add configurable stack size for SMM relocate 2018-10-29 18:01:43 +00:00
Kconfig arch/x86: Drop leftover ROMCC support 2018-06-06 10:28:00 +00:00
Makefile.inc DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INIT 2018-01-15 23:23:17 +00:00