Add support for SPI/flash, LPC/eSPI, MCH and
add pci vendor/product description.
References:
* CPU: Linux kernel
* GPU: Linux kernel
* GPU: https://dgpu-docs.intel.com/devices/hardware-table.html
* Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series
Processors for IoT Applications, February 2023, 636722
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75214
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When parsing XIP stages only compare PT_LOAD phdrs. Currently coreboot
stages only use PT_LOAD phdrs.
Change-Id: I305b25032a3c4a9fdefc76cad77fafdb862a604c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This fixes building inline assembly that uses SIMD registers. This is
for instance the case in the vboot library.
Change-Id: I24fa9d9f81430ea3ecd40de4304a10c6e235fece
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The `handle_range` function in `kconfig_lint` was failing to correctly
handle large hexadecimal values (64-bit value) due to limitations with
Perl's handling of standard integers.
This commit modifies the function to use the `bigint` pragma, enabling
it to handle arbitrarily large integers. This prevents issues with
64-bit hexadecimal values and ensures accurate comparisons for range
validation.
Change-Id: I402bb9bec9ba5bfb79b4185f35228c41d4a7b674
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84575
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot doesn't have a leading zero in gpio < 10.
E.g. G00 -> G0
Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84190
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
IT8613E EC space is divided into 3 banks selectable by EC index 0x06
bits 6:5. Bank0 mostly contains the ITE EC registers known by
coreboot's ITE EC driver. Bank1 contains SB_TSI and PECI temperature
reading registers. Bank2, however, contains additional registers used
to select the temperature source reported in TMPIN reading registers,
PECI bridge registers as well as FAN2-5 controls and extra vectors.
Dump the additional banks using extra-selectors.
Based on non-public IT8613E Preliminary Specification V0.3.
TEST=Perform the IT8613E dump on Hardkernel ODROID H4+.
Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Many sources include device.h and thus static.h, but many only need the
function declarations and type definitions, not the compiled devicetree
from sconfig. This causes many unnecessary recompiles whenever the
devicetree is updated due to the dependency. Address this by moving the
config_of_soc macro directly into the generated static.h header, as it
seems to be the only line in device.h that actually requires static.h.
For now, static.h remains included in device.h so that the build is not
affected. Subsequent commits will include static.h directly into sources
that actually need it, after which it can be dropped from device.h.
Some statistics for C objects:
Dell Latitude E6400 (GM45/ICH9):
669 total objects
181 depend on static.h
2 require static.h
Dell Latitude E6430 (Ivy Bridge/Panther Point):
693 total objects
199 depend on static.h
3 require static.h
Lenovo ThinkCentre M700 / M900 Tiny (Kaby Lake):
794 total objects
298 depend on static.h
23 objects require static.h
MSI PRO Z690-A (WIFI) DDR4 (Alder Lake):
959 total objects
319 depend on static.h
25 require static.h
The number of objects was determined by grepping the build log for
calls to CC, the number of objects that depend on static.h was
determined by grepping for calls to CC after touching static.h, and the
number of objects that actually require the static.h related lines from
device.h was determined by grepping for objects that failed to build
after removing the static.h lines from device.h and running make with
the --keep-going flag.
Change-Id: I7c40135bf2815093b81e47201c38b7d0a6ac8fa8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Previously, Add_gpl() was only used with C and ASL source code files,
and was hard coded to use the C /* */ style comment, preventing it from
being used with files with other comment styles. Convert this into a
generic function for adding arbitrary SPDX license identifiers for
arbitrary filetypes. This replaces the hard coded GPL-2.0-or-later
string used in gma-mainboard.ads with a call to the new function.
This is also used to add SPDX headers to Kconfig and Makefile sources;
as previous commits added them to all such files in the tree.
Tested against logs from a Latitude E6430 (Ivy Bridge) and Precision
M6800 (Haswell) to check that license headers that were already being
generated did not change.
Change-Id: I24a1ccd0afb7045e878bf6eaae7a23f828a9240d
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The fields spi_block_size and base_addr of regular PSP header, lookup
and reserved of combo header, are constants. So we
move the setting statements to the creation functions.
Only update the count, size and fletcher in later function
file_dir_header.
TEST=Binary identical test on all AMD SOC platforms
Change-Id: I55c400e45536a57841b01d7c90d3fef9afa53e78
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
TEST=Binary identical test on all AMD SOC platform with use_combo
Change-Id: I41c5c6fb5acf92604dd06becf1eda680a1fab545
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84131
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The new layout definition has a new way to support combo.
It packs multiple ISH entries into PSP L1 directory.
TEST=Identical test on all AMD platform
Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This just orders the EXCLUDED_DIRS directories in a row based manner,
since there are quite a few them now and it is arguably easier to read
and to add new directories if they are written in a row based fashion.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I802aece355bba4900e71824d802c4b2438726e84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
ifdtool will exit with success while encountering an unrecognized flag.
For example, -g is a newly introduced flag, when we want to call it with
an older version of ifdtool, we will get the return value 0 and cause
confusion.
This patch change the exit status for unrecognized flags and doesn't
change the exit status for -h and -?.
BUG=b:362983041
BRANCH=none
TEST=futility update --servo --image /var/tmp/image.bin --quirks
unlock_csme on the servo host with old ifdtool
Signed-off-by: Hsuan Ting Chen <roccochen@google.com>
Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Currently, cbfstool prints the following error message when the added
file doesn't fit in the region:
E: Could not add [file, 1024 bytes (1 KB)@0x0]; too big?
It requires manual inspection to know the space left in the region. To
make that easier, also print the maximum empty CBFS entry size in the
error message:
E: Could not add file [header 76 + content 1024 bytes (1 KB)] @0x0;
Largest empty slot: 512 bytes
Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The Max size of L2 table is 0x400. If we set it to other value, the
the A/B recovery image can not boot on Cezanne/Majolica platform.
The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards
are binary identical. Tested on Skyrim and image can boot.
Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows better debugging of the build by writing all the commands
run by the build into a file by replacing the standard shell.
Run with:
make SHELL="${PWD}/util/scripts/capture_commands.sh"
This will allow us to verify that the commands being run are posix
compliant.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I67efc5096747c2e746642639f88273132e070e49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This allows clang to link x86 bare metal targets.
TESTED: Qemu i440fx and q35 boot to payload with both 32 and 64bit code
compiled with clang and LTO enabled with updated linker script.
Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84032
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Introduce a sandybridge-style devicetree setting for SPD addresses,
and use it instead of runtime code in mb_get_spd_map() for all
haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all
boards except google/slippy.
Patch also covers recently added Z97 boards using Broadwell MRC.
Also update util/autoport to match.
abuild passes for all affected boards.
autoport builds, but otherwise untested.
Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current region_end() implementation is susceptible to overflow
if the region is at the end of the addressable space. A common case
with the memory-mapped flash of x86 directly below the 32-bit limit.
Note: This patch also changes console output to inclusive limits.
IMO, to the better.
Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When fw_config is unprovisioned (eg. in the factory), devices that do
not have any probe list are enabled by default and those that have probe
list are disabled. On mainboards that support multiple types of boot
critical devices (eg. storage) through probing fw_config, all of
them are disabled when fw_config is unprovisioned. Hence the devices do
not boot to OS. Add sconfig fw_config rule `probe unprovisioned` to
enable such devices when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I178f821e077912776d654971924d67203a7c43df
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83983
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
The USB IDs of the EHCI rate matching hubs found in these chipsets were
missing, preventing the utility from detecting connected USB devices.
Change-Id: I52858e2c75e8a3e1424a13bcddc2f5ec1216164b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This adds some error handling to the code that adds the input segments
(e.g. kernel, cmdline, initrd...) to the output file.
Currently the compress function can fail and coreboot will still
build "successfully" leaving whoever build coreboot puzzled.
Change-Id: Ie36ad469c73cb3ff9360acc9bbe66c245e8b4a1e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83617
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Compressing the already compressed bzImage does not yield any
fruit. If you are lucky it actually makes the image a little bit
smaller. If you are unlucky the image actually gets bigger and since the
compressing function is not checked for any errors, coreboot just builds
successfully even though the payload is broken through compression.
Before this patch you could possibly get this error during compilation:
```
E: LZMA: LzmaEnc_Encode failed 9.
```
and your linux payload would end up something like this in CBFS:
```
FMAP REGION: COREBOOT
Name Offset Type Size Comp
....
fallback/payload 0x1c9c0 simple elf 511 none
....
```
That doesn't stop coreboot from finishing the build though, since we
currently don't check for errors from the compression. That is an issue
for another patch though.
Tested:
Build and run QEMU-Q35 with Linux bzImage as payload.
Change-Id: I022982667515ce721d98af534414d9e336b5f35a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83615
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These settings are not a must, but nice to have. The most noteworthy
setting is `sleep-inactive-ac-type`, which is set to `nothing` so that
the target doesn't go into suspend when AC is used as power supply and
it's unused for a while.
Change-Id: I9a6e3eb88427f94f504a6b991a98b1b51e11bc19
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
PipeWire is the successor of PulseAudio. So use that instead.
Change-Id: Ib557925e481ab72a31a64c4bf353a261dff4296d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83851
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
We introduce two new functions to create region objects. They allow us
to check for integer overflows (region_create_untrusted()) or assert
their absence (region_create()).
This fixes potential overflows in region_overlap() checks in SMI
handlers, where we would wrongfully report MMIO as *not* overlapping
SMRAM.
Also, two cases of strtol() in parse_region() (cbfstool), where the
results were implicitly converted to `size_t`, are replaced with the
unsigned strtoul().
FIT payload support is left out, as it doesn't use the region API
(only the struct).
Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b
Ticket: https://ticket.coreboot.org/issues/522
Found-by: Vadim Zaliva <lord@digamma.ai>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Required for building grub2.
BUG=N/A
TEST=Build successfully for 'QEMU x86 i440fx/piix4' with GRUB2 payload.
Change-Id: I97860f33dd3fde2f6db2f005d65b53cd669403e9
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83676
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch add support for PTL platform to the `spd_tools`.
This would be useful to create dynamic SPD for fatcat variants.
BUG=b:347669091
TEST=Able to generate SPD for LP5 DRAM part.
Change-Id: I55c3f49439fb1ad961c6866f03594431e54279b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83822
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
The parameter is not available for binutils older than 2.39. So move it
to xcompile to provide backwards compatibility for a bit.
Change-Id: I02982769ae2c356f037a747e85d155368bfcb730
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add support to specify the base and size of the replay-protected
monotonic counter (RPMC) non-volatile storage area in the SPI flash. A
later patch will use this to tell amdfwtool about the location and size
of the corresponding FMAP section.
This code is ported from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idafa7d9bf64125bcabd9b47e77147bcffee739e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83812
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The compressing and decompressing functions return 0 on success and not
the other way around.
Change-Id: I9f8653aa805c62eb4bfc3560d7880921830c2c59
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83616
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Sandy/Ivy Bridge boards, this results in northbridge devices ending
up north of (above) southbridge devices. Which is the convention pretty
much all boards in the tree uses.
Change-Id: I9dc2ff13182ff9d92141b1736796749cea49d23a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Running autoport as root has the annoying side effect of making all
generated files owned by root. Prevent this by using sudo to invoke
log-making programs (lspci, dmidecode, acpidump, inteltool, ectool,
superiotool). These programs either need to be run as root or allow
collecting more information if run as root (lspci).
In case there's a valid reason not to use sudo, provide a prompt to
let autoport run the programs directly, as it originally did. There
might be someone trying to run autoport from an OS that lacks sudo.
Change-Id: I4bf4ddf8dd2cb930e9b7303e2ea986d8c072aa7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The original approach to call external programs was rather convoluted
and would fall back to running executables inside the current working
directory if running them from the location specified in the code did
not succeed, swallowing any errors from the first invocation.
Rewrite the system around the `LogMakingProgram` concept, a struct to
represent a program. Each program has a name, prefixes to try running
it from and the arguments to pass to it (if any). Plus, collect error
information from failed executions, but only show it when none of the
prefixes resulted in a successful invocation.
In addition, look for programs in PATH instead of CWD: it is unlikely
that all utils will be in the CWD, but utils can be in the PATH after
one installs them (`sudo make install`). For coreboot utils, look for
them in the utils folder first as the installed versions might not be
up-to-date.
Furthermore, print out the command about to be executed, as there are
some commands (e.g. `ectool` on boards without an EC) that can take a
very long time to complete.
Change-Id: I144bdf609e0aebd8f6ddebc0eb1216bedebfa313
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82403
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to detect more issues in our code, make GCC more picky by
enabling -Wextra. Disable a couple of warnings turned on by -Wextra
temporarily in order to keep everything compiling and working for now.
The warnings may be enabled step by step later.
Since xcompiles applies to coreboot and libpayload, add Wextra here
instead of the top-level Makefile.mk.
Change-Id: I60915cb66581dc2c9b6807335fd0e214b45e76d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83347
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the 'domain' element of the 'domain_path' struct to 'domain_id'
to clarify that this element is the domain ID.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83677
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Some chips (fintek [1,2]) have registers with specific selector-fields
that can affect the address space of the device (for example, switch the
register bank). At the same time, these registers contain fields that
should not change after they are configured in BIOS (for example, set
the port to 2E/2F or 4E/4F). In this case, the selector should take into
account the mask of the register fields and there is no convenient and
easy way to add this in the code in the utility. The selector-fields
should be set manually before the dump and this action is done several
times.
This patch adds an extra-selector mechanism that allows superiotool to
make a correct dump in automatic mode.
Just add a structure with an index, mask, and value for the selector
inside the superio_registers chip for the corresponding LDN to switch
the register bank:
{FINTEK_F81966_DID, "F81962/F81964/F81966/F81967", {
* * *
{NOLDN, "Global",
{0x28,0x2a,0x2b,0x2c,EOT},
{0x00,0x00,0x00,0x00,EOT},
{.idx = 0x27, .mask = 0xd, .val = 0x1} /* update extra selector */
},
{0x03, "LPT",
{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
{NANA,0x03,0x78,0x07,0x03,0xc2,EOT} /* without extra selector */
},
* * *
Tested with Fintek F81966 on Asrock IMB-1222:
- run superiotool on Ubuntu and dump the registers for the board with
the vendor's firmware;
- add the superio chip initialization code to the board configuration
in coreboot and build the project;
- boot Ubuntu on the board with coreboot and re-dump the registers;
- the register values from the board configuration code are the same
in both dumps.
Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e
(Global) -- ESEL[27h] 0x00 (Port Select Register) --
idx 02 07 20 21 23 24 25 26 27 28 29 2a 2b 2c 2d
val 00 0b 15 02 19 34 5a 23 80 a0 f0 45 02 e3 2e
def NA 00 15 02 19 34 00 23 02 a0 00 00 02 0c 28
* * *
The changes do not affect the configuration of existing chips, which
was tested on the Asrock H110-STX motherboard with Nuvoton NCT5539D
(the dump before and after the changes are the same).
[1] CB:83004
[2] CB:83019
Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As of commit 3f0bb2fb07 (autoport: Add support for Haswell-Lynx Point
platform), autoport supports Haswell in addition to Sandy Bridge and Ivy
Bridge.
Change-Id: Iccc10441389580ff8e89c3718484d25d20970f68
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It looks like some unused artifact: The PPC64 Makefile.mk doesn't
pick it up. Also, the only other architecture using this (x86) has
linker flags there, not compiler flags.
Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
