diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 014d939160..2bc0daaf94 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -501,6 +501,12 @@ config BOARD_GOOGLE_PUJJONIRU select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE +config BOARD_GOOGLE_PUJJOCENTO + select BOARD_GOOGLE_BASEBOARD_TRULO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS + config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -861,6 +867,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_PUJJOGATWIN default 0x0 if BOARD_GOOGLE_MELIKS default 0x0 if BOARD_GOOGLE_EPIC + default 0x0 if BOARD_GOOGLE_PUJJOCENTO config DRIVER_TPM_I2C_ADDR hex @@ -946,6 +953,7 @@ config TPM_TIS_ACPI_INTERRUPT default 13 if BOARD_GOOGLE_PUJJOGATWIN default 13 if BOARD_GOOGLE_MELIKS default 13 if BOARD_GOOGLE_EPIC + default 13 if BOARD_GOOGLE_PUJJOCENTO config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN @@ -1039,6 +1047,7 @@ config MAINBOARD_PART_NUMBER default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN default "Meliks" if BOARD_GOOGLE_MELIKS default "Epic" if BOARD_GOOGLE_EPIC + default "Pujjocento" if BOARD_GOOGLE_PUJJOCENTO config VARIANT_DIR default "agah" if BOARD_GOOGLE_AGAH @@ -1117,6 +1126,7 @@ config VARIANT_DIR default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN default "meliks" if BOARD_GOOGLE_MELIKS default "epic" if BOARD_GOOGLE_EPIC + default "pujjocento" if BOARD_GOOGLE_PUJJOCENTO config VBOOT select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 5431cba4c3..764226ddf8 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -229,3 +229,6 @@ config BOARD_GOOGLE_MELIKS config BOARD_GOOGLE_EPIC bool "-> Epic" + +config BOARD_GOOGLE_PUJJOCENTO + bool "-> Pujjocento" diff --git a/src/mainboard/google/brya/variants/pujjocento/Makefile.mk b/src/mainboard/google/brya/variants/pujjocento/Makefile.mk new file mode 100644 index 0000000000..f265e04132 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c new file mode 100644 index 0000000000..488038b9aa --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c @@ -0,0 +1,491 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A0 thru A4, A9 and A10 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_SOC_D0_EC */ + /* A1 : ESPI_IO1 ==> ESPI_SOC_D1_EC */ + /* A2 : ESPI_IO2 ==> ESPI_SOC_D2_EC */ + /* A3 : ESPI_IO3 ==> ESPI_SOC_D3_EC */ + /* A4 : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */ + /* A5 : ESPI_ALERT0# ==> NC */ + PAD_NC(GPP_A5, NONE), + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : NC ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : ESPI_CLK ==> ESPI_SOC_CLK */ + /* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */ + /* A11 : SOC_PD1_INT */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + /* A12 : SOC_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* A14 : USB_OC1# */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> NC */ + PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG), + /* A17 : NC */ + PAD_NC(GPP_A17, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> SOC_HDMI_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + /* A23 : GPP_A23 ==> NC */ + PAD_NC(GPP_A23, NONE), + + /* B0 : CORE_VID0 ==> VCCIN_AUX_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 ==> VCCIN_AUX_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> GYRO_SENSOR_INT */ + PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> ACC_SENSOR_INT */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT), + /* B5 : GPP_B5 ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1), + /* B6 : GPP_B6 ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1), + /* B7 : I2C3_SDA ==> SOC_I2C_SAR_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : I2C3_SCL ==> SOC_I2C_SAR_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B9 : Not available */ + PAD_NC(GPP_B9, NONE), + /* B10 : Not available */ + PAD_NC(GPP_B10, NONE), + /* B11 : SOC_PD0_INT# */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12 : SLP_S0# ==> PM_SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG), + /* B14 : ACZ_SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* B15 : NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + /* B16 : GPP_B16 ==> I2C_TOUCHPAD_SDA */ + PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), + /* B17 : GPP_B17 ==> I2C_TOUCHPAD_SCL */ + PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), + /* B18 : GPP_B18 ==> GPP_B18_STRAP */ + PAD_NC(GPP_B18, NONE), + /* B19 : Not available */ + PAD_NC(GPP_B19, NONE), + /* B20 : Not available */ + PAD_NC(GPP_B20, NONE), + /* B21 : Not available */ + PAD_NC(GPP_B21, NONE), + /* B22 : Not available */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : EN_PP3300_UCAM_X */ + PAD_CFG_GPO_LOCK(GPP_C3, 1, LOCK_CONFIG), + /* C4 : TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), + /* C5 : SML0ALERT# ==> GPP_C5_STRAP */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1_SMBCLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7 : SML1_SMBDATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + + /* D0 : NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> SOC_GSEN2_INT# */ + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + /* D2 : NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> WCAM_RST_L */ + PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), + /* D9 : NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */ + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D11 : NC */ + PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), + /* D13 : UART0_ISH_RX_DBG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : UART0_ISH_TX_DBG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */ + PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */ + PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG), + /* D17 : NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* D18 : NC */ + PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), + /* D19 : I2S_MCLK1_OUT ==> NC */ + PAD_NC(GPP_D19, NONE), + + /* E0 : SOC_PEN_DETECT_R_ODL */ + PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH), + /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */ + PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG), + /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ + PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), + /* E3 : PROC_GP0 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E3, NONE, DEEP), + /* E4 : NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : NC */ + PAD_NC(GPP_E5, NONE), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), + /* E7 : NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8 ==> WLAN_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), + /* E9 : NC */ + PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), + /* E10 : EN_PP3300_WLAN_X */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* E11 : TCHSCR_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* E13 : THC0_SPI1_IO0 ==> SINGLE CHANNEL*/ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* E14 : DDSP_HPDA ==> EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : NC */ + PAD_NC(GPP_E15, NONE), + /* E16 : NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), + /* E18 : NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), + /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WLAN_WWAN_COEX_3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPP_F7 ==> GPP_F7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : Not available */ + PAD_NC(GPP_F8, NONE), + /* F9 : Not available */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPP_F10 ==> GPP_F10_STRAP */ + PAD_NC(GPP_F10, NONE), + /* F11 : NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT), + /* F15 : NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), + /* F19 : Not available */ + PAD_NC(GPP_F19, NONE), + /* F20 : Not available */ + PAD_NC(GPP_F20, NONE), + /* F21 : Not available */ + PAD_NC(GPP_F21, NONE), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPP_H0_STRAP */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPP_H1_STRAP */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPP_H2_STRAP */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG), + /* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : MIPI_WCAM_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : MIPI_WCAM_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : GPP_H12 ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : GPP_H13 ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H14 : Not available */ + PAD_NC(GPP_H14, NONE), + /* H15 : DDPB_CTRLCLK ==> SOC_DP2_CTRL_CLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H16 : Not available */ + PAD_NC(GPP_H16, NONE), + /* H17 : DDPB_CTRLDATA ==> SOC_DP2_CTRL_DATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : SAR_INT_L */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : HDA_BCLK ==> HDA_BIT_CLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* R1 : HDA_SYNC ==> HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), + /* R2 : HDA_SDO ==> HDA_SDOUT */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), + /* R3 : HDA_SDI0 ==> HDA_SDIN0 */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), + /* R4 : HDA_RST# ==> HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* R5 : HDA_SDI1 ==> HDA_SDIN1 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1), + /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* S0 : I2S_SPK_BCLK_R ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : I2S_SPK_LRCK_R ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : DMIC_CKL_A0 ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC_DATA0 ==> NC */ + PAD_NC(GPP_S3, NONE), + /* S4 : NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : NC */ + PAD_NC(GPP_S7, NONE), + + /* I5 : NC */ + PAD_NC(GPP_I5, NONE), + /* I7 : EMMC_CMD ==> NC */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_DATA0 ==> NC */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_DATA1 ==> NC */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_DATA2 ==> NC */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_DATA3 ==> NC */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_DATA4 ==> NC */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_DATA5 ==> NC */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_DATA6 ==> NC */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_DATA7 ==> NC */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK ==> NC */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_I18, NONE), + + /* GPD0 : BATLOW# ==> SOC_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1 : ACPRESENT ==> SOC_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2 : EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT), + /* GPD3 : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4 : SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5 : SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6 : SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD7 : GPD7_STRAP */ + PAD_NC(GPD7, NONE), + /* GPD8 : SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9 : NC */ + PAD_NC(GPD9, NONE), + /* GPD10 : SLP_S5# ==> NC */ + PAD_NC(GPD10, NONE), + /* GPD11 : NC */ + PAD_NC(GPD11, NONE), + + /* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */ + /* vCNV_BT_UART_TXD */ + PAD_NC(GPP_VGPIO_6, NONE), + /* vCNV_BT_UART_RXD */ + PAD_NC(GPP_VGPIO_7, NONE), + /* vCNV_BT_UART_CTS_B */ + PAD_NC(GPP_VGPIO_8, NONE), + /* vCNV_BT_UART_RTS_B */ + PAD_NC(GPP_VGPIO_9, NONE), + + /* Configure the unused vUART for Bluetooth pads to NC mode. */ + /* vUART0_TXD */ + PAD_NC(GPP_VGPIO_18, NONE), + /* vUART0_RXD */ + PAD_NC(GPP_VGPIO_19, NONE), + /* vUART0_CTS_B */ + PAD_NC(GPP_VGPIO_20, NONE), + /* vUART0_RTS_B */ + PAD_NC(GPP_VGPIO_21, NONE), + + /* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E3 : PROC_GP0 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* E13 : THC0_SPI1_IO0 ==> SINGLE CHANNEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), +}; + +/* Fill romstage gpio configuration */ +static const struct pad_config romstage_gpio_table[] = { +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/pujjocento/hda_verb.c b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c new file mode 100644 index 0000000000..bf998e1f0c --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0x10ec12ac, // Subsystem ID + 0x00000013, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting - 1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default (used for headset) + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h new file mode 100644 index 0000000000..be080eb46e --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define WWAN_RST GPP_E17 +#define T2_OFF_MS 20 +#define SLP_S0_HDMI_EN GPP_A7 +#endif diff --git a/src/mainboard/google/brya/variants/pujjocento/memory.c b/src/mainboard/google/brya/variants/pujjocento/memory.c new file mode 100644 index 0000000000..bb80ee15ec --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/memory.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg variant_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &variant_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + return true; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk new file mode 100644 index 0000000000..c60f5439fe --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjocento/memory src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = K3KL8L80CM-MGCT diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt new file mode 100644 index 0000000000..94e605c7b2 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjocento/memory src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +K3KL6L60GM-MGCT 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +H58G56CK8BX146 2 (0010) +K3KL8L80CM-MGCT 3 (0011) diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt new file mode 100644 index 0000000000..e38d99697d --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt @@ -0,0 +1,15 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +K3KL6L60GM-MGCT +H9JCNNNBK3MLYR-N6E +H58G56CK8BX146 +K3KL8L80CM-MGCT diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb new file mode 100644 index 0000000000..4a9ae54d8a --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -0,0 +1,513 @@ +fw_config + field WIFI 3 4 + option WIFI_CNVI_WIFI6E 0 + option WIFI_PCIE_WIFI7 1 + option WIFI_UNKNOWN 2 + end + field THERMAL_SOLUTION 9 9 + option THERMAL_SOLUTION_6W 0 + option THERMAL_SOLUTION_15W 1 + end + field PDC_CONTROL 11 12 + option PDC_CONTROL_UNKNOWN 0 + option PDC_RTS_BYPASS 1 + option PDC_TI_BYPASS 2 + end +end + +chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_H" + register "pmc_gpe0_dw2" = "GPP_F" + + # S0ix enable + register "s0ix_enable" = "true" + + # DPTF enable + register "dptf_enable" = "true" + + register "tcc_offset" = "10" # TCC of 90 + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch) + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch) + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch) + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE) + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + # FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 0, + }" + + # Enable CNVi BT Audio offload + register "cnvi_bt_audio_offload" = "1" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # FIXME: To be enabled in future based on PNP impact data. + # Disable Package C-state demotion for nissa baseboard. + register "disable_package_c_state_demotion" = "true" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 150, + .scl_hcnt = 85, + .sda_hold = 35, + } + }, + }" + + device domain 0 on + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 60), + TEMP_PCT(39, 55), + TEMP_PCT(38, 50), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 60), + TEMP_PCT(50, 55), + TEMP_PCT(48, 50), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 5000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 0 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_6W + end + end + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 58), + TEMP_PCT(39, 53), + TEMP_PCT(38, 47), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 58), + TEMP_PCT(50, 53), + TEMP_PCT(48, 47), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 14000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 1 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_15W + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""PCIe Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on + probe WIFI WIFI_PCIE_WIFI7 + probe WIFI WIFI_UNKNOWN + end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on + probe WIFI WIFI_CNVI_WIFI6E + probe WIFI WIFI_UNKNOWN + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WLAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + probe WIFI WIFI_CNVI_WIFI6E + probe WIFI WIFI_UNKNOWN + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + # # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E10)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + probe WIFI WIFI_PCIE_WIFI7 + probe WIFI WIFI_UNKNOWN + end + + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end #I2C0 + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 0x15 on end + end + end + device ref heci1 on end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref pmc hidden end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/pujjocento/variant.c b/src/mainboard/google/brya/variants/pujjocento/variant.c new file mode 100644 index 0000000000..d202cbd110 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjocento/variant.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) + || fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + config->cnvi_bt_audio_offload = true; + } else { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + config->cnvi_bt_audio_offload = false; + } +} + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(SLP_S0_HDMI_EN); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(SLP_S0_HDMI_EN); +}