diff --git a/src/soc/mediatek/common/include/soc/mt6359p.h b/src/soc/mediatek/common/include/soc/mt6359p.h
index 017e6c8d61..a2e50638ae 100644
--- a/src/soc/mediatek/common/include/soc/mt6359p.h
+++ b/src/soc/mediatek/common/include/soc/mt6359p.h
@@ -35,12 +35,14 @@ enum {
 	PMIC_VSRAM_PROC1_ELR	= 0x1b44,
 	PMIC_VSRAM_PROC2_ELR	= 0x1b46,
 	PMIC_VSRAM_MD_ELR	= 0x1b4a,
+	PMIC_VCN18_CON0		= 0x1c2e,
 	PMIC_VSIM1_CON0		= 0x1cd0,
 	PMIC_VM18_CON0		= 0x1d88,
 	PMIC_VSRAM_PROC1_VOSEL1	= 0x1e90,
 	PMIC_VSRAM_PROC2_VOSEL1	= 0x1eb0,
 	PMIC_VSRAM_MD_VOSEL1	= 0x1f36,
 	PMIC_VSIM1_ANA_CON0	= 0x1fa2,
+	PMIC_VCN18_ANA_CON0	= 0x2010,
 	PMIC_VM18_ANA_CON0	= 0x2020,
 };
 
@@ -68,6 +70,7 @@ enum {
 	MT6359P_VM18,
 	MT6359P_VMODEM,
 	MT6359P_VSRAM_MD,
+	MT6359P_VCN18,
 	MT6359P_MAX,
 };
 
@@ -78,6 +81,11 @@ enum {
 #define VM18_VOL_REG_SHIFT  8
 #define VM18_VOL_OFFSET 600
 
+#define VCN18_VOL_UV_MAX	1900000
+#define VCN18_VOL_UV_MIN	1800000
+#define VCN18_VOL_MV_OFFSET	600
+#define VCN18_VOL_SHIFT		8
+
 #define EFUSE_WAIT_US 5000
 #define EFUSE_BUSY 1
 
@@ -90,9 +98,12 @@ void mt6359p_set_vm18_voltage(u32 vm18_uv);
 u32 mt6359p_get_vm18_voltage(void);
 void mt6359p_set_vsim1_voltage(u32 vsim1_uv);
 u32 mt6359p_get_vsim1_voltage(void);
+void mt6359p_set_vcn18_voltage(u32 vcn18_uv);
+u32 mt6359p_get_vcn18_voltage(void);
 void mt6359p_enable_vpa(bool enable);
 void mt6359p_enable_vsim1(bool enable);
 void mt6359p_enable_vm18(bool enable);
+void mt6359p_enable_vcn18(bool enable);
 void mt6359p_init_pmif_arb(void);
 u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift);
 void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift);
diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h
index 3cec8f06eb..152ba34d7b 100644
--- a/src/soc/mediatek/common/include/soc/regulator.h
+++ b/src/soc/mediatek/common/include/soc/regulator.h
@@ -21,6 +21,7 @@ enum mtk_regulator {
 	MTK_REGULATOR_VSRAM_PROC11,
 	MTK_REGULATOR_VSRAM_PROC12,
 	MTK_REGULATOR_VRF12,
+	MTK_REGULATOR_VCN18,
 	MTK_REGULATOR_VCN33,
 	MTK_REGULATOR_VDD18,
 	MTK_REGULATOR_VIO18,
diff --git a/src/soc/mediatek/common/mt6359p.c b/src/soc/mediatek/common/mt6359p.c
index 8026f29915..5dad6a44cb 100644
--- a/src/soc/mediatek/common/mt6359p.c
+++ b/src/soc/mediatek/common/mt6359p.c
@@ -336,6 +336,34 @@ u32 mt6359p_get_vsim1_voltage(void)
 	return 1000 * (reg_offset + reg_vol + reg_cali);
 }
 
+u32 mt6359p_get_vcn18_voltage(void)
+{
+	u32 reg_vol, reg_cali;
+	if (!pmif_arb)
+		die("[%s] ERROR: pmif_arb not initialized", __func__);
+
+	reg_vol = 100 * mt6359p_read_field(PMIC_VCN18_ANA_CON0, 0xF, VCN18_VOL_SHIFT);
+	reg_cali = 10 * mt6359p_read_field(PMIC_VCN18_ANA_CON0, 0xF, 0);
+	return 1000 * (VCN18_VOL_MV_OFFSET + reg_vol + reg_cali);
+}
+
+void mt6359p_set_vcn18_voltage(u32 vcn18_uv)
+{
+	u32 reg_vol, reg_cali;
+	if (!pmif_arb)
+		die("[%s] ERROR: pmif_arb not initialized", __func__);
+
+	if (vcn18_uv < VCN18_VOL_UV_MIN || vcn18_uv > VCN18_VOL_UV_MAX) {
+		printk(BIOS_ERR,
+		       "%s: VCN18 voltage %d is out of range (%d uV - %d uV)\n",
+		       __func__, vcn18_uv, VCN18_VOL_UV_MIN, VCN18_VOL_UV_MAX);
+		return;
+	}
+	reg_vol = (vcn18_uv / 1000 - VCN18_VOL_MV_OFFSET) / 100;
+	reg_cali = (vcn18_uv / 1000) % 100 / 10;
+	mt6359p_write(PMIC_VCN18_ANA_CON0, (reg_vol << VCN18_VOL_SHIFT) | reg_cali);
+}
+
 void mt6359p_enable_vpa(bool enable)
 {
 	mt6359p_write_field(PMIC_VPA_CON0, enable, 0x1, 0);
@@ -351,6 +379,11 @@ void mt6359p_enable_vm18(bool enable)
 	mt6359p_write_field(PMIC_VM18_CON0, enable, 0x1, 0);
 }
 
+void mt6359p_enable_vcn18(bool enable)
+{
+	mt6359p_write_field(PMIC_VCN18_CON0, enable, 0x1, 0);
+}
+
 void mt6359p_init_pmif_arb(void)
 {
 	if (pmif_arb)