From fc88b6217433429ec93c7e0ca4b677669d2fd3a8 Mon Sep 17 00:00:00 2001 From: Uwe Poeche Date: Mon, 7 Jul 2025 16:21:33 +0200 Subject: [PATCH] mb/siemens/mc_ehl6: Enable PCIe root ports and clocks Configure and enable the PCIe root ports and associated clocks for the mc_ehl6 mainboard. This is necessary because the PCIe configuration differs from the mc_ehl2 baseboard. TEST=Boot into the OS and verify that all expected PCIe devices are correctly detected. Change-Id: Ie5ac3d437088d1db08f869317ef3e5712c3baa3e Signed-off-by: Uwe Poeche Reviewed-on: https://review.coreboot.org/c/coreboot/+/90082 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- .../siemens/mc_ehl/variants/mc_ehl6/devicetree.cb | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb index 67ece6d158..1e5bd881c0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb @@ -40,12 +40,12 @@ chip soc/intel/elkhartlake register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" @@ -55,11 +55,17 @@ chip soc/intel/elkhartlake register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports + register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports + register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" + register "PcieRpLtrDisable[2]" = "true" + register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[6]" = "true" # Storage (SDCARD/EMMC) related UPDs @@ -176,7 +182,10 @@ chip soc/intel/elkhartlake device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD + device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.4 on end # RP5 (pcie1 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE)