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mb/google/brox/var/lotso: Decrease cpu power limits

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Based on RPL 15W baseline, PL4 should set to 87W.
Ref: 686872_RPL_UPH_RPL_UH_R_Power_Map_Rev2p4p1.xlsm

BUG=b:404416910
TEST=emerge-brox coreboot chromeos-bootimage
     cbmem -c | grep PL shows PL4=87

Change-Id: Ief8c4e5b119dc334f3b469a046946f95a070b866
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jian Tong 2025-07-20 14:54:31 +08:00 • committed by Subrata Banik
commit fbb0738272
2 changed files with 3 additions and 3 deletions
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2
src/mainboard/google/brox/variants/lotso/overridetree.cb
View file

@ -75,7 +75,7 @@ chip soc/intel/alderlake
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 25,
.tdp_pl4 = 114,
.tdp_pl4 = 87,
}"
device domain 0 on

4
src/mainboard/google/brox/variants/lotso/ramstage.c
View file

@ -19,7 +19,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
.pl1_max_power = 15000,
.pl2_min_power = 25000,
.pl2_max_power = 25000,
.pl4_power = 114000
.pl4_power = 87000
},
{
.mchid = PCI_DID_INTEL_RPL_P_ID_4,
@ -28,7 +28,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
.pl1_max_power = 15000,
.pl2_min_power = 25000,
.pl2_max_power = 25000,
.pl4_power = 114000
.pl4_power = 87000
},
};