diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index c6007b1269..f3c8107169 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -75,7 +75,7 @@ chip soc/intel/alderlake
 	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,
-		.tdp_pl4 = 114,
+		.tdp_pl4 = 87,
 	}"
 
 	device domain 0 on
diff --git a/src/mainboard/google/brox/variants/lotso/ramstage.c b/src/mainboard/google/brox/variants/lotso/ramstage.c
index 80276607be..d8de83fb08 100644
--- a/src/mainboard/google/brox/variants/lotso/ramstage.c
+++ b/src/mainboard/google/brox/variants/lotso/ramstage.c
@@ -19,7 +19,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
 		.pl1_max_power = 15000,
 		.pl2_min_power = 25000,
 		.pl2_max_power = 25000,
-		.pl4_power = 114000
+		.pl4_power = 87000
 	},
 	{
 		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
@@ -28,7 +28,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
 		.pl1_max_power = 15000,
 		.pl2_min_power = 25000,
 		.pl2_max_power = 25000,
-		.pl4_power = 114000
+		.pl4_power = 87000
 	},
 };