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soc/intel/skl: Allow disabling CLKREQ# independently of SrcClk

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On Skylake mainboards, enablement of the Source Clock of a PCIe Root
Port is currently dependent on enablement of CLKREQ# in the devicetree.

However it may be desirable to disable CLKREQ# but still keep the Source
Clock enabled.  Specifically, that's the recommended workaround for
erratum 47 of Sunrise Point-LP PCHs, which concerns exit instability from
ASPM L1 state:

   "disable the associated PCH SRCCLKREQ# signal to keep the PCIe clock
    active during L1"
    https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf

Therefore, key Source Clock enablement off of Root Port enablement in
the devicetree, rather than CLKREQ# enablement.  A subsequent commit
takes advantage of this to implement the workaround on Google Pixelbook
Eve mainboards.

Change-Id: I9b69357c59bad3392da85e0629a9d368524daffd
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Lukas Wunner 2026-02-15 14:43:49 +01:00 • committed by Matt DeVillier
commit faf12bcacd
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/skylake/chip.c
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@ -310,8 +310,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* all the enabled PCIe root ports, invalid(0x1F) is set for
* disabled PCIe root ports.
*/
u32 enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
if (config->PcieRpClkReqSupport[i])
if (enable_mask & BIT(i))
params->PcieRpClkSrcNumber[i] =
config->PcieRpClkSrcNumber[i];
else