From faf12bcacdb777f4cc949a9d17d86dd44e4e6c4c Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Sun, 15 Feb 2026 14:43:49 +0100 Subject: [PATCH] soc/intel/skl: Allow disabling CLKREQ# independently of SrcClk On Skylake mainboards, enablement of the Source Clock of a PCIe Root Port is currently dependent on enablement of CLKREQ# in the devicetree. However it may be desirable to disable CLKREQ# but still keep the Source Clock enabled. Specifically, that's the recommended workaround for erratum 47 of Sunrise Point-LP PCHs, which concerns exit instability from ASPM L1 state: "disable the associated PCH SRCCLKREQ# signal to keep the PCIe clock active during L1" https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf Therefore, key Source Clock enablement off of Root Port enablement in the devicetree, rather than CLKREQ# enablement. A subsequent commit takes advantage of this to implement the workaround on Google Pixelbook Eve mainboards. Change-Id: I9b69357c59bad3392da85e0629a9d368524daffd Signed-off-by: Lukas Wunner Reviewed-on: https://review.coreboot.org/c/coreboot/+/91650 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/intel/skylake/chip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a884035f59..964c1264aa 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -310,8 +310,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * all the enabled PCIe root ports, invalid(0x1F) is set for * disabled PCIe root ports. */ + u32 enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { - if (config->PcieRpClkReqSupport[i]) + if (enable_mask & BIT(i)) params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i]; else