From fad9878a3e11d7b6f302022b010d1dd59fc45c11 Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Fri, 12 Dec 2025 21:03:26 +0530
Subject: [PATCH] vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to
 FSP WCL.3393.02

Update Wildcatlake FSP headers from version WCL.3393.02

FspmUpd.h: Add below upds
* Vdd2HVoltage
* Vdd1Voltage
* Vdd2LVoltage
* VddqVoltage

FspsUpd.h: Add below upds
* UfsInlineEncryption
* MaxActiveDisplays

MemInfoHob.h:
* PprTargetedStatus - PPR status of each Targeted PPR request

BUG=b:464402767
TEST=Able to build google/ocelot with the latest header changes

Change-Id: I66f22452fb7cd771752afe8bd7c0c3e5dac2106e
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../intel/fsp/fsp2_0/wildcatlake/FspmUpd.h    | 26 ++++++++++++++++++-
 .../intel/fsp/fsp2_0/wildcatlake/FspsUpd.h    | 22 +++++++++++++---
 .../intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h |  4 +++
 3 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
index dace75895d..661948e325 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
@@ -3121,7 +3121,31 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved93[55];
+  UINT8                       Reserved93[17];
+
+/** Offset 0x0B42 - VDD2 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2HVoltage;
+
+/** Offset 0x0B44 - VDD1 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd1Voltage;
+
+/** Offset 0x0B46 - VDD2L Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2LVoltage;
+
+/** Offset 0x0B48 - VDDQ Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      VddqVoltage;
+
+/** Offset 0x0B4A - Reserved
+**/
+  UINT8                       Reserved94[30];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
index b5194418b1..ae0ffe29dd 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
@@ -458,9 +458,17 @@ typedef struct {
 **/
   UINT8                       UfsEnable[2];
 
-/** Offset 0x014D - Reserved
+/** Offset 0x014D - UFS Inline Encryption enable/disable
+  Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
+  to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption
+  for controller 1
+  $EN_DIS
 **/
-  UINT8                       Reserved12[4];
+  UINT8                       UfsInlineEncryption[2];
+
+/** Offset 0x014F - Reserved
+**/
+  UINT8                       Reserved12[2];
 
 /** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
   Enable/Disable PCIe tunneling for USB4, default is enable
@@ -2026,9 +2034,15 @@ typedef struct {
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x1401 - Reserved
+/** Offset 0x1401 - Select MaxActiveDisplays
+  Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported
+  is 2 displays only
 **/
-  UINT8                       Reserved50[67];
+  UINT8                       MaxActiveDisplays;
+
+/** Offset 0x1402 - Reserved
+**/
+  UINT8                       Reserved50[66];
 
 /** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
index 83e346ca5c..c89cf2cab1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
@@ -35,6 +35,9 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
 #define _MAX_RANK_IN_CHANNEL       (4)       ///< The maximum number of ranks per channel.
 #define _MAX_SDRAM_IN_DIMM         (5)       ///< The maximum number of SDRAMs per DIMM.
 
+// Must match the corresponding definition in CMrcExtTypes.h
+#define PPR_REQUEST_MAX           (2)
+
 // Must match definitions in
 // Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
 #define HOB_MAX_SAGV_POINTS 4
@@ -359,6 +362,7 @@ typedef struct {
   BOOLEAN           MixedEccDimms;                     ///< TRUE if both ECC and nonECC Dimms were detected in the system
   UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
   UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
+  BOOLEAN           PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
 } MEMORY_INFO_DATA_HOB;
 
 /**