From fa2e54907b0c7a155da771213f918c065b717c19 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 28 Jan 2026 18:09:19 -0600 Subject: [PATCH] mb/google/brya: Mark PCIe root ports with attached eMMC as built-in Set the PCIE_RP_BUILT_IN flag on the PCIe root ports which have eMMC attached via a GL9763E bridge/controller for all variants using PCIe- attached eMMC. This ensures the FSP PcieRpSlotImplemented UPD is set properly and that FSP correctly treats these RPs as built-in rather than slot devices. TEST=tested with rest of patch train Change-Id: Ifb4b255ea5367733405a7ac5d73c616ce7f8aad5 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/90980 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Sean Rhodes --- src/mainboard/google/brya/variants/anahera/overridetree.cb | 2 +- src/mainboard/google/brya/variants/anahera4es/overridetree.cb | 2 +- src/mainboard/google/brya/variants/aurash/overridetree.cb | 2 +- src/mainboard/google/brya/variants/crota/overridetree.cb | 2 +- src/mainboard/google/brya/variants/gladios/overridetree.cb | 2 +- src/mainboard/google/brya/variants/kinox/overridetree.cb | 2 +- src/mainboard/google/brya/variants/lisbon/overridetree.cb | 2 +- src/mainboard/google/brya/variants/moli/overridetree.cb | 2 +- src/mainboard/google/brya/variants/primus/overridetree.cb | 2 +- src/mainboard/google/brya/variants/taeko/overridetree.cb | 2 +- src/mainboard/google/brya/variants/taniks/overridetree.cb | 2 +- src/mainboard/google/brya/variants/volmar/overridetree.cb | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 12566087db..b0dfb81526 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -202,7 +202,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 6, .clk_req = 6, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" end #PCIE7 EMMC device ref tcss_dma0 on diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 33daa9962c..41393781c7 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -184,7 +184,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 6, .clk_req = 6, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" end #PCIE7 EMMC device ref tcss_dma0 on diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index a18197627c..0d2cd9974b 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -193,7 +193,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(12)]" = "{ .clk_src = 1, .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" probe STORAGE STORAGE_EMMC probe STORAGE STORAGE_UNKNOWN diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index a55c68c98e..a7994127c1 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -203,7 +203,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 1, .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" end #PCIE3 BH799BB device ref pcie_rp9 off end diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 6c3eaf952a..10b54c4f92 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -213,7 +213,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(12)]" = "{ .clk_src = 4, .clk_req = 4, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" probe STORAGE STORAGE_EMMC end #PCIE12 EMMC diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index d0740b339d..5b708f08f7 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -261,7 +261,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(6)]" = "{ .clk_src = 1, .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 6c3eaf952a..10b54c4f92 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -213,7 +213,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(12)]" = "{ .clk_src = 4, .clk_req = 4, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" probe STORAGE STORAGE_EMMC end #PCIE12 EMMC diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 3397d0c211..741d54d748 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -201,7 +201,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(12)]" = "{ .clk_src = 1, .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" probe STORAGE STORAGE_EMMC probe STORAGE STORAGE_UNKNOWN diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index b2619ee67d..f073184ed4 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -183,7 +183,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 6, .clk_req = 6, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" end #PCIE3 BH799BB device ref tcss_dma0 on diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 0e1290f873..0abad554cc 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -565,7 +565,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, .pcie_rp_aspm = ASPM_L1, }" probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index e11793ae4e..09654293dc 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -383,7 +383,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index f57b733931..2145204245 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -331,7 +331,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 4, .clk_req = 4, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, }" probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end #PCIE3 BH799BB