From f941b51e0e3cb2570a855984edfdd134a48f9d3f Mon Sep 17 00:00:00 2001 From: Irving-CH Lin Date: Wed, 11 Jun 2025 11:58:15 +0800 Subject: [PATCH] soc/mediatek/mt8189: Correct MFG MUX OPP init setting Set the default MFG MUX OPP (Operating Performance Point) from 0 (mfg_sel) to 1 (mfgpll), as mfgpll is used in normal operation and mfg_sel is only needed during DVFS transitions. Also enable glitch-free configuration for mfgpll to improve PLL stability. BUG=b:399571996 BRANCH=none TEST=Change GPU DVFS by below commands: echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/min_freq echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/max_freq And then check PLL and MUX register values are correct. Signed-off-by: Irving-CH lin Change-Id: I285cc5f07facbb23a448151ceb6c1d037753432c Reviewed-on: https://review.coreboot.org/c/coreboot/+/88090 Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8189/pll.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c index 84fb16347d..ffd48987e4 100644 --- a/src/soc/mediatek/mt8189/pll.c +++ b/src/soc/mediatek/mt8189/pll.c @@ -559,6 +559,7 @@ void mt_pll_init(void) write32(&mtk_apmixed->apll1_tuner_con0, 0x6F28BD4D); write32(&mtk_apmixed->apll2_tuner_con0, 0x78FD5266); setbits32(&mtk_apmixed->emipll_con[0], BIT(8)); + setbits32(&mtk_apmixed->mfgpll_con[0], BIT(8)); /* PLL all enable */ write32(&mtk_apmixed->pllen_all_set, 0x0007FFFC); @@ -622,7 +623,7 @@ void mt_pll_post_init(void) /* TOPCKGEN CG Clear */ write32(&mtk_topckgen->clk_misc_cfg_3.clr, 0x00010000); - write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3CFCFF); + write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3DFCFF); /* INFRACFG_AO CG Clear */ write32(&mtk_infracfg_ao->infracfg_ao_module_cg_0_clr, 0x10000000); write32(&mtk_infracfg_ao->infracfg_ao_module_cg_1_clr, 0x21000000);