erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Mickey: Update LPDDR3 configuration

Browse source 
This makes the same changes to the LPDDR3 configuration that
were made for Samsung modules:
- Enable ODT function
- Change DS to 40 Ω from 34.3 Ω

BUG=chrome-os-partner:47416
BRANCH=firmware-veyron-6588.B
TEST=Boot on mickey elpida board

Change-Id: I2d54d3087ecd3536469866f30e4eb2d8b1acd5c1
Signed-off-by: jiazi Yang <Tomato_Yang@asus.com>
Reviewed-on: https://chromium-review.googlesource.com/311153
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
jiazi Yang 2015-11-09 14:07:31 +08:00 • committed by ChromeOS bot
commit f90eab44c1
5 changed files with 15 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

5
src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-2GB.inc
View file

@ -65,7 +65,8 @@
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
/* 40 Ohms instead of 34.3 due to bad PCB routing on Mickey. */
.mr[3] = 0x2
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
@ -74,5 +75,5 @@
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
.odt = 1
},

5
src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-4GB.inc
View file

@ -65,7 +65,8 @@
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
/* 40 Ohms instead of 34.3 due to bad PCB routing on Mickey. */
.mr[3] = 0x2
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
@ -74,5 +75,5 @@
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
.odt = 1
},

5
src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc
View file

@ -65,7 +65,8 @@
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
/* 40 Ohms instead of 34.3 due to bad PCB routing on Mickey. */
.mr[3] = 0x2
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
@ -74,5 +75,5 @@
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
.odt = 1,
},

5
src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-4GB.inc
View file

@ -64,7 +64,8 @@
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
/* 40 Ohms instead of 34.3 due to bad PCB routing on Mickey. */
.mr[3] = 0x2
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
@ -73,5 +74,5 @@
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
.odt = 1,
},

5
src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB.inc
View file

@ -64,7 +64,8 @@
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
/* 40 Ohms instead of 34.3 due to bad PCB routing on Mickey. */
.mr[3] = 0x2
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
@ -73,5 +74,5 @@
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
.odt = 1,
},