diff --git a/src/soc/intel/broadwell/broadwell/pci_devs.h b/src/soc/intel/broadwell/broadwell/pci_devs.h
index 9c3dd06640..76e3a688ed 100644
--- a/src/soc/intel/broadwell/broadwell/pci_devs.h
+++ b/src/soc/intel/broadwell/broadwell/pci_devs.h
@@ -20,6 +20,9 @@
 #ifndef _BROADWELL_PCI_DEVS_H_
 #define _BROADWELL_PCI_DEVS_H_
 
+#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEVFN(slot,func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
 #if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
 #include <arch/io.h>
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
@@ -27,43 +30,90 @@
 #else
 #include <device/device.h>
 #include <device/pci_def.h>
-#define _SA_DEV(slot)		dev_find_slot(0, \
-					PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0))
-#define _PCH_DEV(slot,func)	dev_find_slot(0, \
-					PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func))
+#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _PCH_DEV(slot,func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
-#define SA_DEV_SLOT_IGD		0x02
-#define SA_DEV_SLOT_MINIHD	0x03
+#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
+#define  SA_DEV_ROOT		_SA_DEV(ROOT)
 
-#define SA_DEV_ROOT		_SA_DEV(ROOT)
-#define SA_DEV_IGD		_SA_DEV(IGD)
-#define SA_DEV_MINIHD		_SA_DEV(MINIHD)
+#define SA_DEV_SLOT_IGD		0x02
+#define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
+#define  SA_DEV_IGD		_SA_DEV(IGD)
+
+#define SA_DEV_SLOT_MINIHD	0x03
+#define  SA_DEVFN_MINIHD	_SA_DEVFN(MINIHD)
+#define  SA_DEV_MINIHD		_SA_DEV(MINIHD)
 
 /* PCH Devices */
 
-#define PCH_DEV_SLOT_XHCI	0x14
-#define PCH_DEV_SLOT_SIO	0x15
-#define PCH_DEV_SLOT_ME		0x16
-#define PCH_DEV_SLOT_HDA	0x1b
-#define PCH_DEV_SLOT_PCIE	0x1c
-#define PCH_DEV_SLOT_EHCI	0x1d
-#define PCH_DEV_SLOT_LPC	0x1f
+#define PCH_DEV_SLOT_ADSP	0x13
+#define  PCH_DEVFN_ADSP		_PCH_DEVFN(ADSP, 0)
+#define  PCH_DEV_ADSP		_PCH_DEV(ADSP, 0)
 
-#define PCH_DEV_XHCI		_PCH_DEV(XHCI, 0)
-#define PCH_DEV_UART0		_PCH_DEV(UART0, 0)
-#define PCH_DEV_UART1		_PCH_DEV(UART1, 0)
-#define PCH_DEV_ME		_PCH_DEV(ME, 0)
-#define PCH_DEV_HDA		_PCH_DEV(HDA, 0)
-#define PCH_DEV_EHCI		_PCH_DEV(EHCI, 0)
-#define PCH_DEV_LPC		_PCH_DEV(LPC, 0)
-#define PCH_DEV_IDE		_PCH_DEV(LPC, 1)
-#define PCH_DEV_SATA		_PCH_DEV(LPC, 2)
-#define PCH_DEV_SMBUS		_PCH_DEV(LPC, 3)
-#define PCH_DEV_SATA2		_PCH_DEV(LPC, 5)
-#define PCH_DEV_THERMAL		_PCH_DEV(LPC, 6)
+#define PCH_DEV_SLOT_XHCI	0x14
+#define  PCH_DEVFN_XHCI		_PCH_DEVFN(XHCI, 0)
+#define  PCH_DEV_XHCI		_PCH_DEV(XHCI, 0)
+
+#define PCH_DEV_SLOT_SIO	0x15
+#define  PCH_DEV_SDMA		_PCH_DEV(SIO, 0)
+#define  PCH_DEV_I2C0		_PCH_DEV(SIO, 1)
+#define  PCH_DEV_I2C1		_PCH_DEV(SIO, 2)
+#define  PCH_DEV_SPI0		_PCH_DEV(SIO, 3)
+#define  PCH_DEV_SPI1		_PCH_DEV(SIO, 4)
+#define  PCH_DEV_UART0		_PCH_DEV(SIO, 5)
+#define  PCH_DEV_UART1		_PCH_DEV(SIO, 6)
+#define  PCH_DEVFN_SDMA		_PCH_DEVFN(SIO, 0)
+#define  PCH_DEVFN_I2C0		_PCH_DEVFN(SIO, 1)
+#define  PCH_DEVFN_I2C1		_PCH_DEVFN(SIO, 2)
+#define  PCH_DEVFN_SPI0		_PCH_DEVFN(SIO, 3)
+#define  PCH_DEVFN_SPI1		_PCH_DEVFN(SIO, 4)
+#define  PCH_DEVFN_UART0	_PCH_DEVFN(SIO, 5)
+#define  PCH_DEVFN_UART1	_PCH_DEVFN(SIO, 6)
+
+#define PCH_DEV_SLOT_ME		0x16
+#define  PCH_DEVFN_ME		_PCH_DEVFN(ME, 0)
+#define  PCH_DEVFN_ME_2		_PCH_DEVFN(ME, 1)
+#define  PCH_DEVFN_ME_IDER	_PCH_DEVFN(ME, 2)
+#define  PCH_DEVFN_ME_KT	_PCH_DEVFN(ME, 3)
+#define  PCH_DEV_ME		_PCH_DEV(ME, 0)
+#define  PCH_DEV_ME_2		_PCH_DEV(ME, 1)
+#define  PCH_DEV_ME_IDER	_PCH_DEV(ME, 2)
+#define  PCH_DEV_ME_KT		_PCH_DEV(ME, 3)
+
+#define PCH_DEV_SLOT_SDIO	0x17
+#define  PCH_DEVFN_SDIO		_PCH_DEVFN(SDIO, 0)
+#define  PCH_DEV_SDIO		_PCH_DEV(SDIO, 0)
+
+#define PCH_DEV_SLOT_GBE	0x19
+#define  PCH_DEVFN_GBE		_PCH_DEVFN(GBE, 0)
+#define  PCH_DEV_GBE		_PCH_DEV(GBE, 0)
+
+#define PCH_DEV_SLOT_HDA	0x1b
+#define  PCH_DEVFN_HDA		_PCH_DEVFN(HDA, 0)
+#define  PCH_DEV_HDA		_PCH_DEV(HDA, 0)
+
+#define PCH_DEV_SLOT_PCIE	0x1c
+
+#define PCH_DEV_SLOT_EHCI	0x1d
+#define  PCH_DEVFN_EHCI		_PCH_DEVFN(EHCI, 0)
+#define  PCH_DEV_EHCI		_PCH_DEV(EHCI, 0)
+
+#define PCH_DEV_SLOT_LPC	0x1f
+#define  PCH_DEVFN_LPC		_PCH_DEVFN(LPC, 0)
+#define  PCH_DEVFN_IDE		_PCH_DEVFN(LPC, 1)
+#define  PCH_DEVFN_SATA		_PCH_DEVFN(LPC, 2)
+#define  PCH_DEVFN_SMBUS	_PCH_DEVFN(LPC, 3)
+#define  PCH_DEVFN_SATA2	_PCH_DEVFN(LPC, 5)
+#define  PCH_DEVFN_THERMAL	_PCH_DEVFN(LPC, 6)
+#define  PCH_DEV_LPC		_PCH_DEV(LPC, 0)
+#define  PCH_DEV_IDE		_PCH_DEV(LPC, 1)
+#define  PCH_DEV_SATA		_PCH_DEV(LPC, 2)
+#define  PCH_DEV_SMBUS		_PCH_DEV(LPC, 3)
+#define  PCH_DEV_SATA2		_PCH_DEV(LPC, 5)
+#define  PCH_DEV_THERMAL	_PCH_DEV(LPC, 6)
 
 #endif
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index b9667cc38c..efb109e832 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -92,91 +92,88 @@ static void pch_enable_d3hot(device_t dev)
 void pch_disable_devfn(device_t dev)
 {
 	switch (dev->path.pci.devfn) {
-	case PCI_DEVFN(19, 0): /* Audio DSP */
+	case PCH_DEVFN_ADSP: /* Audio DSP */
 		RCBA32_OR(FD, PCH_DISABLE_ADSPD);
 		break;
-	case PCI_DEVFN(20, 0): /* XHCI */
+	case PCH_DEVFN_XHCI: /* XHCI */
 		RCBA32_OR(FD, PCH_DISABLE_XHCI);
 		break;
-	case PCI_DEVFN(21, 0): /* DMA */
+	case PCH_DEVFN_SDMA: /* DMA */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(21, 1): /* I2C0 */
+	case PCH_DEVFN_I2C0: /* I2C0 */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(21, 2): /* I2C1 */
+	case PCH_DEVFN_I2C1: /* I2C1 */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(21, 3): /* SPI0 */
+	case PCH_DEVFN_SPI0: /* SPI0 */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(21, 4): /* SPI1 */
+	case PCH_DEVFN_SPI1: /* SPI1 */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(21, 5): /* UART0 */
+	case PCH_DEVFN_UART0: /* UART0 */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(21, 6): /* UART1 */
+	case PCH_DEVFN_UART1: /* UART1 */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(22, 0): /* MEI #1 */
+	case PCH_DEVFN_ME: /* MEI #1 */
 		RCBA32_OR(FD2, PCH_DISABLE_MEI1);
 		break;
-	case PCI_DEVFN(22, 1): /* MEI #2 */
+	case PCH_DEVFN_ME_2: /* MEI #2 */
 		RCBA32_OR(FD2, PCH_DISABLE_MEI2);
 		break;
-	case PCI_DEVFN(22, 2): /* IDE-R */
+	case PCH_DEVFN_ME_IDER: /* IDE-R */
 		RCBA32_OR(FD2, PCH_DISABLE_IDER);
 		break;
-	case PCI_DEVFN(22, 3): /* KT */
+	case PCH_DEVFN_ME_KT: /* KT */
 		RCBA32_OR(FD2, PCH_DISABLE_KT);
 		break;
-	case PCI_DEVFN(23, 0): /* SDIO */
+	case PCH_DEVFN_SDIO: /* SDIO */
 		pch_enable_d3hot(dev);
 		pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 		break;
-	case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
+	case PCH_DEVFN_GBE: /* Gigabit Ethernet */
 		RCBA32_OR(BUC, PCH_DISABLE_GBE);
 		break;
-	case PCI_DEVFN(26, 0): /* EHCI #2 */
-		RCBA32_OR(FD, PCH_DISABLE_EHCI2);
-		break;
-	case PCI_DEVFN(27, 0): /* HD Audio Controller */
+	case PCH_DEVFN_HDA: /* HD Audio Controller */
 		RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
 		break;
-	case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
-	case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
-	case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
-	case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
-	case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
-	case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
-	case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
-	case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 0): /* PCI Express Root Port 1 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 1): /* PCI Express Root Port 2 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 2): /* PCI Express Root Port 3 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 3): /* PCI Express Root Port 4 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 4): /* PCI Express Root Port 5 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 5): /* PCI Express Root Port 6 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 6): /* PCI Express Root Port 7 */
+	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 7): /* PCI Express Root Port 8 */
 		RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
 		break;
-	case PCI_DEVFN(29, 0): /* EHCI #1 */
+	case PCH_DEVFN_EHCI: /* EHCI #1 */
 		RCBA32_OR(FD, PCH_DISABLE_EHCI1);
 		break;
-	case PCI_DEVFN(31, 0): /* LPC */
+	case PCH_DEVFN_LPC: /* LPC */
 		RCBA32_OR(FD, PCH_DISABLE_LPC);
 		break;
-	case PCI_DEVFN(31, 2): /* SATA #1 */
+	case PCH_DEVFN_SATA: /* SATA #1 */
 		RCBA32_OR(FD, PCH_DISABLE_SATA1);
 		break;
-	case PCI_DEVFN(31, 3): /* SMBUS */
+	case PCH_DEVFN_SMBUS: /* SMBUS */
 		RCBA32_OR(FD, PCH_DISABLE_SMBUS);
 		break;
-	case PCI_DEVFN(31, 5): /* SATA #2 */
+	case PCH_DEVFN_SATA2: /* SATA #2 */
 		RCBA32_OR(FD, PCH_DISABLE_SATA2);
 		break;
-	case PCI_DEVFN(31, 6): /* Thermal Subsystem */
+	case PCH_DEVFN_THERMAL: /* Thermal Subsystem */
 		RCBA32_OR(FD, PCH_DISABLE_THERMAL);
 		break;
 	}
@@ -186,13 +183,12 @@ void broadwell_pch_enable_dev(device_t dev)
 {
 	u32 reg32;
 
-	/* PCH PCIe Root Ports are handled in PCIe driver. */
-	if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_PCIE)
-		return;
-
-	/* EHCI disable is handled in ramstage driver */
-	if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_EHCI)
+	/* These devices need special enable/disable handling */
+	switch (PCI_SLOT(dev->path.pci.devfn)) {
+	case PCH_DEV_SLOT_PCIE:
+	case PCH_DEV_SLOT_EHCI:
 		return;
+	}
 
 	if (!dev->enabled) {
 		printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index e3ce28a231..97d9d2f7d8 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -27,6 +27,7 @@
 #include <stdlib.h>
 #include <broadwell/iobp.h>
 #include <broadwell/nvs.h>
+#include <broadwell/pci_devs.h>
 #include <broadwell/pch.h>
 #include <broadwell/ramstage.h>
 #include <broadwell/rcba.h>
@@ -45,9 +46,9 @@ static int serialio_uart_is_debug(struct device *dev)
 {
 #if CONFIG_INTEL_PCH_UART_CONSOLE
 	switch (dev->path.pci.devfn) {
-	case PCI_DEVFN(21, 5): /* UART0 */
+	case PCH_DEVFN_UART0: /* UART0 */
 		return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0);
-	case PCI_DEVFN(21, 6): /* UART1 */
+	case PCH_DEVFN_UART1: /* UART1 */
 		return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1);
 	}
 #endif
@@ -195,57 +196,57 @@ static void serialio_init(struct device *dev)
 
 	if (!config->sio_acpi_mode)
 		serialio_enable_clock(bar0);
-	else if (dev->path.pci.devfn != PCI_DEVFN(21, 0))
+	else if (dev->path.pci.devfn != PCH_DEVFN_SDMA)
 		serialio_enable_d3hot(dev); /* all but SDMA */
 
 	switch (dev->path.pci.devfn) {
-	case PCI_DEVFN(21, 0): /* SDMA */
+	case PCH_DEVFN_SDMA: /* SDMA */
 		sio_index = SIO_ID_SDMA;
 		serialio_init_once(config->sio_acpi_mode);
 		serialio_d21_mode(sio_index, SIO_PIN_INTB,
 				  config->sio_acpi_mode);
 		break;
-	case PCI_DEVFN(21, 1): /* I2C0 */
+	case PCH_DEVFN_I2C0: /* I2C0 */
 		sio_index = SIO_ID_I2C0;
 		serialio_d21_ltr(bar0);
 		serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
 		serialio_d21_mode(sio_index, SIO_PIN_INTC,
 				  config->sio_acpi_mode);
 		break;
-	case PCI_DEVFN(21, 2): /* I2C1 */
+	case PCH_DEVFN_I2C1: /* I2C1 */
 		sio_index = SIO_ID_I2C1;
 		serialio_d21_ltr(bar0);
 		serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
 		serialio_d21_mode(sio_index, SIO_PIN_INTC,
 				  config->sio_acpi_mode);
 		break;
-	case PCI_DEVFN(21, 3): /* SPI0 */
+	case PCH_DEVFN_SPI0: /* SPI0 */
 		sio_index = SIO_ID_SPI0;
 		serialio_d21_ltr(bar0);
 		serialio_d21_mode(sio_index, SIO_PIN_INTC,
 				  config->sio_acpi_mode);
 		break;
-	case PCI_DEVFN(21, 4): /* SPI1 */
+	case PCH_DEVFN_SPI1: /* SPI1 */
 		sio_index = SIO_ID_SPI1;
 		serialio_d21_ltr(bar0);
 		serialio_d21_mode(sio_index, SIO_PIN_INTC,
 				  config->sio_acpi_mode);
 		break;
-	case PCI_DEVFN(21, 5): /* UART0 */
+	case PCH_DEVFN_UART0: /* UART0 */
 		sio_index = SIO_ID_UART0;
 		if (!serialio_uart_is_debug(dev))
 			serialio_d21_ltr(bar0);
 		serialio_d21_mode(sio_index, SIO_PIN_INTD,
 				  config->sio_acpi_mode);
 		break;
-	case PCI_DEVFN(21, 6): /* UART1 */
+	case PCH_DEVFN_UART1: /* UART1 */
 		sio_index = SIO_ID_UART1;
 		if (!serialio_uart_is_debug(dev))
 			serialio_d21_ltr(bar0);
 		serialio_d21_mode(sio_index, SIO_PIN_INTD,
 				  config->sio_acpi_mode);
 		break;
-	case PCI_DEVFN(23, 0): /* SDIO */
+	case PCH_DEVFN_SDIO: /* SDIO */
 		sio_index = SIO_ID_SDIO;
 		serialio_d23_ltr(bar0);
 		serialio_d23_mode(config->sio_acpi_mode);