diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a63df081a8..2c3723afa6 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4687,6 +4687,8 @@
 #define PCI_DID_INTEL_WCL_ID_1			0xfd00
 #define PCI_DID_INTEL_WCL_ID_2			0xfd01
 #define PCI_DID_INTEL_WCL_ID_3			0xfd02
+#define PCI_DID_INTEL_WCL_ID_4			0xfd03
+#define PCI_DID_INTEL_WCL_ID_5			0xfd04
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 2939a065fa..18708eb7f4 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -63,6 +63,17 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
+	# Reference: 858124 Power Delivery Guide Rev1p0, 830097 Powermap Rev1p1
+	# fast_vmode_i_trip values are derived from ICCMax with a safety margin.
+	# ITRIP_NOM is approximately 0.70 of ICCMax
+	# TODO: Update with actual i_trip values.
+
+	register "fast_vmode_i_trip[WCL_CORE]" = "{
+		[VR_DOMAIN_IA] = 35 * 4,
+		[VR_DOMAIN_GT] = 35 * 4,
+		[VR_DOMAIN_SA] = 24 * 4
+	}"
+
 	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 30acf30f49..749e9c6ad9 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -428,6 +428,8 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_WCL_ID_3,
+	PCI_DID_INTEL_WCL_ID_4,
+	PCI_DID_INTEL_WCL_ID_5,
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_U_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_3,
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index d6cae4afad..30639d5668 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -44,6 +44,8 @@ static struct {
 	{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_3, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_4, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_5, "Wildcatlake" },
 };
 
 static struct {
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index e9a73a1635..c837ec6da9 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -58,6 +58,7 @@ enum soc_intel_pantherlake_power_limits {
 	PTL_H_1_CORE,
 	PTL_H_2_CORE,
 	PTL_H_3_CORE,
+	WCL_CORE,
 	PTL_POWER_LIMITS_COUNT,
 };
 
@@ -74,7 +75,12 @@ enum soc_intel_pantherlake_sku {
 	PTL_H484_SKU,
 	PTL_H4XE_SKU,
 	PTL_H204_SKU,
-	MAX_PTL_SKUS
+	WCL_SKU_1,
+	WCL_SKU_2,
+	WCL_SKU_3,
+	WCL_SKU_4,
+	WCL_SKU_5,
+	MAX_PTL_SKUS,
 };
 
 /* Mapping of different SKUs based on CPU ID and TDP values */
@@ -98,6 +104,11 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
+	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
+	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
+	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4},
+	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5},
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index c5f1d2bd11..31abe5be94 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -2,7 +2,11 @@ chip soc/intel/pantherlake
 
 	device cpu_cluster 0 on end
 
-	# TODO: Add WCL power limits
+	register "power_limits_config[WCL_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 93,
+	}"
 
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"