From f6926dc8a5a93c37f475b33f6eec9fade607d871 Mon Sep 17 00:00:00 2001 From: Qinghong Zeng Date: Tue, 6 May 2025 15:24:57 +0800 Subject: [PATCH] mb/google/nissa/var/pujjoniru: Update DTT settings for thermal control update DTT settings for thermal control, according to b:395802079#comment37. BUG=b:395802079 TEST=emerge-nissa coreboot Change-Id: Ia3d27baf31f2ba684d3bd8f84e19ce802c3b68d1 Signed-off-by: Qinghong Zeng Reviewed-on: https://review.coreboot.org/c/coreboot/+/87545 Reviewed-by: Weimin Wu Reviewed-by: Subrata Banik Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- .../google/brya/variants/pujjoniru/overridetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb index cc3d1dcefc..418ac6db60 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb @@ -102,8 +102,8 @@ chip soc/intel/alderlake }" register "power_limits_config[ADL_N_081_15W_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 25, + .tdp_pl1_override = 22, + .tdp_pl2_override = 35, .tdp_pl4 = 114, }" @@ -279,15 +279,15 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 12000, - .max_power = 15000, + .min_power = 15000, + .max_power = 22000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 }, .pl2 = { - .min_power = 25000, - .max_power = 25000, + .min_power = 35000, + .max_power = 35000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000