soc/intel/cannonlake: Hook up DPTF device to devicetree

Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`. For boards where the
register setting and PCI device status are not in agreement, use
the register setting to determine the PCI device status, since that
is what FSP uses.

Modeled after similar patches for other SoCs.

Change-Id: If17e6e86f6933b334e13f2c05ca513cef0998996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87483
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/chip.h

@@ -220,8 +220,6 @@ struct soc_intel_cannonlake_config {
 	/* Gfx related */
 	bool SkipExtGfxScan;
 
-	bool Device4Enable;
-
 	/* CPU PL2/4 Config
 	 * Performance: Maximum PLs for maximum performance.
 	 * Baseline: Baseline PLs for balanced performance at lower power.

src/soc/intel/cannonlake/fsp_params.c

@@ -631,7 +631,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 * the `Heci1Disabled` UPD to `0`.
 	 */
 	s_cfg->Heci1Disabled = 0;
-	s_cfg->Device4Enable = config->Device4Enable;
+	s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_TS);
 
 	/* Teton Glacier hybrid storage support */
 	s_cfg->TetonGlacierMode = config->TetonGlacierMode;