diff --git a/src/soc/mediatek/common/dp/dptx_hal_v1.c b/src/soc/mediatek/common/dp/dptx_hal_v1.c index 91fbddf692..1bf9b71bb4 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_v1.c +++ b/src/soc/mediatek/common/dp/dptx_hal_v1.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -78,24 +79,21 @@ bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp) return mtk_dp_read(mtk_dp, REG_3414_DP_TRANS_P0) & BIT(2); } -bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, - u8 swing_value, u8 preemphasis) +void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, + u8 *swing_value, u8 *preemphasis) { - printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n", - lane_num, swing_value, preemphasis); + assert(lane_count <= DPTX_LANE_MAX); - if (lane_num >= DPTX_LANE_MAX) { - printk(BIOS_ERR, "invalid lane number: %d\n", lane_num); - return false; + for (int lane = 0; lane < lane_count; lane++) { + printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n", + lane, swing_value[lane], preemphasis[lane]); + mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP, + swing_value[lane] << volt_swing[lane].shift, + volt_swing[lane].mask); + mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP, + preemphasis[lane] << volt_preemphasis[lane].shift, + volt_preemphasis[lane].mask); } - - mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP, - swing_value << volt_swing[lane_num].shift, - volt_swing[lane_num].mask); - mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP, - preemphasis << volt_preemphasis[lane_num].shift, - volt_preemphasis[lane_num].mask); - return true; } void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c index 7000d89472..0833f2de62 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_v2.c +++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c @@ -86,21 +86,19 @@ bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp) return mtk_dp_read(mtk_dp, REG_364C_AUX_TX_P0) & BIT(15); } -bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, u8 swing_value, - u8 preemphasis) +void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, + u8 *swing_value, u8 *preemphasis) { - assert(lane_num <= DPTX_LANE_MAX); + assert(lane_count <= DPTX_LANE_MAX); - for (int i = 0; i < lane_num; ++i) { - mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], - swing_value << EDP_TX_LN_VOLT_SWING_VAL_SHIFT | - preemphasis << EDP_TX_LN_PRE_EMPH_VAL_SHIFT, - EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK); + for (int lane = 0; lane < lane_count; lane++) { printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n", - i, swing_value, preemphasis); + lane, swing_value[lane], preemphasis[lane]); + mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[lane], + swing_value[lane] << EDP_TX_LN_VOLT_SWING_VAL_SHIFT | + preemphasis[lane] << EDP_TX_LN_PRE_EMPH_VAL_SHIFT, + EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK); } - mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0)); - return true; } void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp) @@ -315,21 +313,6 @@ void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value) mtk_dp_mask(mtk_dp, REG_34A4_DP_TRANS_P0, value << 2, BIT(3) | BIT(2)); } -void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val, - u8 *preemphasis) -{ - assert(lane_count <= DPTX_LANE_MAX); - - for (int i = 0; i < lane_count; ++i) { - mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], - swing_val[i] << EDP_TX_LN_VOLT_SWING_VAL_SHIFT | - preemphasis[i] << EDP_TX_LN_PRE_EMPH_VAL_SHIFT, - EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK); - printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n", - i, swing_val[i], preemphasis[i]); - } -} - void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable) { u32 val = 0x0; diff --git a/src/soc/mediatek/common/dp/dptx_v1.c b/src/soc/mediatek/common/dp/dptx_v1.c index 6cf590d417..7001282128 100644 --- a/src/soc/mediatek/common/dp/dptx_v1.c +++ b/src/soc/mediatek/common/dp/dptx_v1.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -12,112 +13,101 @@ #include #include -static bool dptx_training_checkswingpre(struct mtk_dp *mtk_dp, +static void dptx_training_checkswingpre(struct mtk_dp *mtk_dp, u8 target_lane_count, const u8 *dpcp202_x, u8 *dpcp_buf) { - bool ret = true; - u8 swing_value, preemphasis; + u8 swing_value[DPTX_LANE_MAX] = {0}, preemphasis[DPTX_LANE_MAX] = {0}; + + assert(target_lane_count <= DPTX_LANE_MAX); /* Lane 0 */ if (target_lane_count >= 0x1) { - swing_value = (dpcp202_x[4] & 0x3); - preemphasis = (dpcp202_x[4] & 0xc) >> 2; - - /* Adjust the swing and pre-emphasis */ - ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE0, - swing_value, preemphasis); + swing_value[0] = (dpcp202_x[4] & 0x3); + preemphasis[0] = (dpcp202_x[4] & 0xc) >> 2; /* * Adjust the swing and pre-emphasis done, * and notify sink side. */ - dpcp_buf[0] = swing_value | (preemphasis << 3); + dpcp_buf[0] = swing_value[0] | (preemphasis[0] << 3); /* Max swing reached. */ - if (swing_value == DPTX_SWING3) + if (swing_value[0] == DPTX_SWING3) dpcp_buf[0] |= BIT(2); /* Max pre-emphasis reached. */ - if (preemphasis == DPTX_PREEMPHASIS3) + if (preemphasis[0] == DPTX_PREEMPHASIS3) dpcp_buf[0] |= BIT(5); } /* Lane 1 */ if (target_lane_count >= 0x2) { - swing_value = (dpcp202_x[4] & 0x30) >> 4; - preemphasis = (dpcp202_x[4] & 0xc0) >> 6; - - /* Adjust the swing and pre-emphasis */ - ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE1, - swing_value, preemphasis); + swing_value[1] = (dpcp202_x[4] & 0x30) >> 4; + preemphasis[1] = (dpcp202_x[4] & 0xc0) >> 6; /* * Adjust the swing and pre-emphasis done, * and notify sink side. */ - dpcp_buf[1] = swing_value | (preemphasis << 3); + dpcp_buf[1] = swing_value[1] | (preemphasis[1] << 3); /* Max swing reached. */ - if (swing_value == DPTX_SWING3) + if (swing_value[1] == DPTX_SWING3) dpcp_buf[1] |= BIT(2); /* Max pre-emphasis reached. */ - if (preemphasis == DPTX_PREEMPHASIS3) + if (preemphasis[1] == DPTX_PREEMPHASIS3) dpcp_buf[1] |= BIT(5); } /* Lane 2 and Lane 3 */ - if (target_lane_count == 0x4) { - /* Lane 2 */ - swing_value = (dpcp202_x[5] & 0x3); - preemphasis = (dpcp202_x[5] & 0x0c) >> 2; + if (target_lane_count >= 0x3) { + assert(target_lane_count == 0x4); - /* Adjust the swing and pre-emphasis */ - ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE2, - swing_value, preemphasis); + /* Lane 2 */ + swing_value[2] = (dpcp202_x[5] & 0x3); + preemphasis[2] = (dpcp202_x[5] & 0x0c) >> 2; /* * Adjust the swing and pre-emphasis done, * and notify sink side. */ - dpcp_buf[2] = swing_value | (preemphasis << 3); + dpcp_buf[2] = swing_value[2] | (preemphasis[2] << 3); /* Max swing reached. */ - if (swing_value == DPTX_SWING3) + if (swing_value[2] == DPTX_SWING3) dpcp_buf[2] |= BIT(2); /* Max pre-emphasis reached. */ - if (preemphasis == DPTX_PREEMPHASIS3) + if (preemphasis[2] == DPTX_PREEMPHASIS3) dpcp_buf[2] |= BIT(5); /* Lane 3 */ - swing_value = (dpcp202_x[5] & 0x30) >> 4; - preemphasis = (dpcp202_x[5] & 0xc0) >> 6; - - /* Adjust the swing and pre-emphasis */ - ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE3, - swing_value, preemphasis); + swing_value[3] = (dpcp202_x[5] & 0x30) >> 4; + preemphasis[3] = (dpcp202_x[5] & 0xc0) >> 6; /* * Adjust the swing and pre-emphasis done, * and notify sink side. */ - dpcp_buf[0x3] = swing_value | (preemphasis << 3); + dpcp_buf[0x3] = swing_value[3] | (preemphasis[3] << 3); /* Max swing reached. */ - if (swing_value == DPTX_SWING3) + if (swing_value[3] == DPTX_SWING3) dpcp_buf[3] |= BIT(2); /* Max pre-emphasis reached. */ - if (preemphasis == DPTX_PREEMPHASIS3) + if (preemphasis[3] == DPTX_PREEMPHASIS3) dpcp_buf[3] |= BIT(5); } + /* Adjust the swing and pre-emphasis */ + dptx_hal_set_swing_preemphasis(mtk_dp, target_lane_count, + swing_value, preemphasis); + /* Wait signal stable enough */ mdelay(2); - - return ret; } static int dptx_train_tps1(struct mtk_dp *mtk_dp, u8 target_lanecount, diff --git a/src/soc/mediatek/common/dp/dptx_v2.c b/src/soc/mediatek/common/dp/dptx_v2.c index 80e1f7c33e..ab41b86ed2 100644 --- a/src/soc/mediatek/common/dp/dptx_v2.c +++ b/src/soc/mediatek/common/dp/dptx_v2.c @@ -81,7 +81,7 @@ static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00103 + lane, 0x1, &val); } - dptx_hal_phy_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis); + dptx_hal_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis); } static void dptx_training_changemode(struct mtk_dp *mtk_dp) diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index 9c553181c7..ecd1132bdf 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -62,8 +62,9 @@ bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *rx_buf); bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *data); -bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, - u8 swing_value, u8 preemphasis); +void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count, + u8 *swing_value, u8 *preemphasis); +void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp); u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp); u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset); void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); @@ -73,7 +74,6 @@ void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask); void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); void dptx_hal_verify_clock(struct mtk_dp *mtk_dp); -void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp); void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp); void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable); void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable); diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h index e076915e92..7f49e5608b 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h @@ -24,7 +24,5 @@ void dptx_hal_phy_init(struct mtk_dp *mtk_dp); void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp); void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable); void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count); -void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val, - u8 *preemphasis); #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V2_H */ diff --git a/src/soc/mediatek/mt8196/dptx_hal.c b/src/soc/mediatek/mt8196/dptx_hal.c index f2ec6541b3..110f5f1ada 100644 --- a/src/soc/mediatek/mt8196/dptx_hal.c +++ b/src/soc/mediatek/mt8196/dptx_hal.c @@ -6,7 +6,7 @@ #include #include -static void dptx_hal_phy_reset_swing_preemphasis(struct mtk_dp *mtk_dp) +void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) { for (int i = 0; i < dptx_hal_driving_offset_size; i++) mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], 0, @@ -37,5 +37,5 @@ void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp) printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n", mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0)); - dptx_hal_phy_reset_swing_preemphasis(mtk_dp); + dptx_hal_reset_swing_preemphasis(mtk_dp); }