From f56a936c5441b381a3cbb09ffdef0aa8cef727b0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 18 Mar 2026 13:58:06 +0530 Subject: [PATCH] soc/qualcomm/x1p42100: Allow asynchronous PCIe initialization To support this early hardware initiation, add pcie_common.c and soc-specific pcie.c to the romstage build when SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT and PCI Kconfigs are enabled. This allows the SoC to kick off link training in romstage and verify the link status later in ramstage. BUG=b:449871690 TEST=Able to build and boot google/quenbih. Change-Id: I6f81b88b36f51b55cb47846f9e81d0be8f987825 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/91724 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- src/soc/qualcomm/x1p42100/Makefile.mk | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk index 77412e4cd0..117b8e1e4d 100644 --- a/src/soc/qualcomm/x1p42100/Makefile.mk +++ b/src/soc/qualcomm/x1p42100/Makefile.mk @@ -38,6 +38,10 @@ romstage-y += ../common/aop_load_reset.c romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c romstage-y += ../common/spmi.c romstage-y += pmic.c +ifeq ($(CONFIG_SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT),y) +romstage-$(CONFIG_PCI) += ../common/pcie_common.c +romstage-$(CONFIG_PCI) += pcie.c +endif ################################################################################ ramstage-y += soc.c