add support for failover image. Make example configs actually work
This commit is contained in:
Steven James
parent
71e607a388
commit
f50296e1c8
5 changed files with 67 additions and 197 deletions
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@ -21,11 +21,11 @@ ldscript cpu/i386/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE
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ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE
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#mainboardinit mainboard/intel/sv2/reset32.inc
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#ldscript mainboard/intel/sv2/reset32.lds
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mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE
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ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE
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##
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## Include an id string (For safe flashing)
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@ -43,10 +43,10 @@ ldscript arch/i386/lib/id.lds
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## Things are delicate and we test to see if we should
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## failover to another image.
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#mainboardinit northbridge/intel/82860/reset_test.inc
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#mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE
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#mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE
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#ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
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mainboardinit northbridge/intel/82860/reset_test.inc
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mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE
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mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE
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ldscript mainboard/intel/Clearwater/failover.lds USE_FALLBACK_IMAGE
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###
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### O.k. We aren't just an intermediary anymore!
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@ -179,7 +179,7 @@ option HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option tabe table
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##
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#option HAVE_OPTION_TABLE=1
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option HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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@ -226,7 +226,7 @@ nooption MEMORY_HOLE
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## If we aren't a fallback image we must be a normal image
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## This is useful for optional includes
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##
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option USE_FALLBACK_IMAGE=0
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option USE_FALLBACK_IMAGE=1
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expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE
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###
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@ -244,8 +244,8 @@ option _RAMBASE=0x00008000
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## For the trick of using cache as ram
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## put the fake ram location at this address
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option CACHE_RAM_BASE=0xfff70000
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option CACHE_RAM_SIZE=0x00010000
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#option CACHE_RAM_BASE=0xfff70000
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#option CACHE_RAM_SIZE=0x00010000
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##
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## Use a small 8K stack
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@ -268,7 +268,7 @@ option PYRO_SERIAL=1
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##
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## Only use the option table in a normal image
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##
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#expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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@ -282,14 +282,16 @@ expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE*
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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#expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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expr ZKERNEL_START = 0xfff00000
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expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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#expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE
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expr _ROMBASE = 0xffff0000 - (USE_FALLBACK_IMAGE*0x10000)
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expr _ROMBASE = 0xffff0000 - (USE_NORMAL_IMAGE*0x10000)
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##
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## Compute a range of ROM that can cached to speed of linuxBIOS,
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@ -10,7 +10,7 @@ email: pyro@linuxlabs.com
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status: unstable
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explanation: Too new to claim stable (even though it seems good)
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flash-types: Intel 82802ac8 FWH (8Mbit), 82802ab8 (4Mbit) can be substituted
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payload-types: etherboot, memtest86
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payload-types: etherboot, memtest86, pforth (an embedded Forth environment)
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# e.g. linux, plan 9, wince, etc.
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OS-types: linux
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# e.g. "Plan 9 interrupts don't work on this chipset"
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@ -19,7 +19,7 @@ console-types: serial
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# vga is unsupported, unstable, or stable
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vga: unsupported
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# Last-known-good follows the internationl date standard: day/month/year
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last-known-good: 27/10/2002
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last-known-good: 07/11/2002
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Comments:
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Links:
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Mainboard-revision: 0 (pre-production sample) 1 (production)
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@ -1,104 +1,33 @@
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## This will make a target directory of ./fallback
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## This is relative to where the configuration file resides in the filesystem
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target ./fallback
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# This will make a target directory of ./clearwater1
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# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE
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# CONFIG TOOL. Make it absolute if you like
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target clearwater1
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mainboard supermicro/p4dc6
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# Intel Clearwater (cw2) mainboard
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mainboard intel/Clearwater
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## Build a fallback not a normal image.
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option USE_FALLBACK_IMAGE=1
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## Build an image for a 512KB rom
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## ./fallback/romimage is just the last 64KB which we reserve for the fallback image.
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option ROM_SIZE=524288
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#option ROM_SIZE=1048576
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## Select the maximum size the linuxBIOS code can compile to.
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## Allow linuxBIOS to be up to 48KB in size
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option ROM_IMAGE_SIZE=49152
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##
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### The Serial Console
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##
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## Hardware flow control is currently ignored.
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## Enable the Serial Console
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE=1
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## Select the serial console baud rate.
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option TTYS0_BAUD=115200
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#option TTYS0_BAUD=57600
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#option TTYS0_BAUD=38400
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#option TTYS0_BAUD=19200
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#option TTYS0_BAUD=9600
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#option TTYS0_BAUD=4800
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#option TTYS0_BAUD=2400
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#option TTYS0_BAUD=1200
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE=1
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#option CONFIGURE_L2_CACHE=1
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# Select the serial console base port
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option TTYS0_BASE=0x3f8
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# Use the internal VGA frame buffer device
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#option HAVE_FRAMEBUFFER=1
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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option TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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option DEFAULT_CONSOLE_LOGLEVEL=9
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## At a maximum only compile in this level of debugging
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option MAXIMUM_CONSOLE_LOGLEVEL=6
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## Use the elf bootloader
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option USE_ELF_BOOT=1
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## Select the boot device
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option USE_GENERIC_ROM=1
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#option BOOT_FLOPPY=1
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#option USE_SERIAL_FILL_INBUF=1
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#option BOOT_IDE=1
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# Load etherboot with the elf bootloader
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# The payload command is relative the build directory
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# So .. is the directory this config file resides in
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payload ../eepro100.ebi
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option STD_FLASH=1
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option USE_FALLBACK_IMAGE = 1
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##
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## Cpu Speed
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##
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option CPU_CLOCK_MULTIPLIER=XEON_X8
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#option CPU_CLOCK_MULTIPLIER=XEON_X9
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#option CPU_CLOCK_MULTIPLIER=XEON_X10
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#option CPU_CLOCK_MULTIPLIER=XEON_X11
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#option CPU_CLOCK_MULTIPLIER=XEON_X12
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#option CPU_CLOCK_MULTIPLIER=XEON_X13
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#option CPU_CLOCK_MULTIPLIER=XEON_X14
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#option CPU_CLOCK_MULTIPLIER=XEON_X15
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#option CPU_CLOCK_MULTIPLIER=XEON_X16
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#option CPU_CLOCK_MULTIPLIER=XEON_X17
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#option CPU_CLOCK_MULTIPLIER=XEON_X18
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X20
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#option CPU_CLOCK_MULTIPLIER=XEON_X21
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#option CPU_CLOCK_MULTIPLIER=XEON_X22
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#option CPU_CLOCK_MULTIPLIER=XEON_X23
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option HAVE_PIRQ_TABLE=1
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##
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## Select power on after power fail setting
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option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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option DEFAULT_CONSOLE_LOGLEVEL=8
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#payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf
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@ -1,105 +1,43 @@
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## This will make a target directory of ./normal
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## This is relative to where the configuration file resides in the filesystem
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target ./normal
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# This will make a target directory of ./winfast
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# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE
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# CONFIG TOOL. Make it absolute if you like
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target clearwater-primary
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mainboard supermicro/p4dc6
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# Leadtek WinFast 6300 MAX mainboard
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mainboard intel/Clearwater
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## Build a normal not a fallback image.
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option USE_FALLBACK_IMAGE=0
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## Build an image for a 512KB rom
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## ./normal/romimage is the entire rom image except for the last 64KB
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## which are reserved for the fallback image.
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option ROM_SIZE=524288
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#option ROM_SIZE=1048576
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## Select the maximum size the linuxBIOS code can compile to.
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## Allow linuxBIOS to be up to 48KB in size
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option ROM_IMAGE_SIZE=49152
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##
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### The Serial Console
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##
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## Hardware flow control is currently ignored.
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## Enable the Serial Console
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE=1
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## Select the serial console baud rate.
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option TTYS0_BAUD=115200
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#option TTYS0_BAUD=57600
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#option TTYS0_BAUD=38400
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#option TTYS0_BAUD=19200
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#option TTYS0_BAUD=9600
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#option TTYS0_BAUD=4800
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#option TTYS0_BAUD=2400
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#option TTYS0_BAUD=1200
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE=1
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#option CONFIGURE_L2_CACHE=1
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# Select the serial console base port
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option TTYS0_BASE=0x3f8
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# Use the internal VGA frame buffer device
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#option HAVE_FRAMEBUFFER=1
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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option TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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option DEFAULT_CONSOLE_LOGLEVEL=9
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## At a maximum only compile in this level of debugging
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option MAXIMUM_CONSOLE_LOGLEVEL=8
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## Use the elf bootloader
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option USE_ELF_BOOT=1
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## Select the boot device
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option USE_GENERIC_ROM=1
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#option BOOT_FLOPPY=1
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#option USE_SERIAL_FILL_INBUF=1
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#option BOOT_IDE=1
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# Load etherboot with the elf bootloader
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# The payload command is relative the build directory
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# So .. is the directory this config file resides in
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payload ../eepro100.ebi
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option STD_FLASH=1
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option USE_FALLBACK_IMAGE = 0
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##
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## Cpu Speed
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##
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#option CPU_CLOCK_MULTIPLIER=XEON_X8
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#option CPU_CLOCK_MULTIPLIER=XEON_X9
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#option CPU_CLOCK_MULTIPLIER=XEON_X10
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#option CPU_CLOCK_MULTIPLIER=XEON_X11
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#option CPU_CLOCK_MULTIPLIER=XEON_X12
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#option CPU_CLOCK_MULTIPLIER=XEON_X13
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#option CPU_CLOCK_MULTIPLIER=XEON_X14
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#option CPU_CLOCK_MULTIPLIER=XEON_X15
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#option CPU_CLOCK_MULTIPLIER=XEON_X16
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option CPU_CLOCK_MULTIPLIER=XEON_X17
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#option CPU_CLOCK_MULTIPLIER=XEON_X18
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X20
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#option CPU_CLOCK_MULTIPLIER=XEON_X21
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#option CPU_CLOCK_MULTIPLIER=XEON_X22
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#option CPU_CLOCK_MULTIPLIER=XEON_X23
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option HAVE_PIRQ_TABLE=1
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##
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## Select power on after power fail setting
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option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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option DEFAULT_CONSOLE_LOGLEVEL=8
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payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf
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# Path to your kernel (vmlinux)
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# NOTE; you need a path to your test12 kernel here.
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#linux /usr/src/linux-2.2.17-beoboot-pyro1
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#linux /usr/src/linux-2.4.0-test12
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# Kernel command line parameters
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#commandline root=/dev/nftla1
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# We're using disk on chip. Tell it where to find the docipl code
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#docipl northsouthbridge/sis/630/ipl.S
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1
src/mainboard/intel/Clearwater/failover.lds
Normal file
1
src/mainboard/intel/Clearwater/failover.lds
Normal file
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@ -0,0 +1 @@
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__normal_image = 0xf0000 - 8;
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