From f50296e1c8f4788cc85024ca04b1e4be5e0de700 Mon Sep 17 00:00:00 2001 From: Steven James Date: Thu, 7 Nov 2002 22:03:33 +0000 Subject: [PATCH] add support for failover image. Make example configs actually work --- src/mainboard/intel/Clearwater/Config | 32 ++--- src/mainboard/intel/Clearwater/STATUS | 4 +- .../intel/Clearwater/example-fallback.config | 109 +++------------- .../intel/Clearwater/example-normal.config | 120 +++++------------- src/mainboard/intel/Clearwater/failover.lds | 1 + 5 files changed, 68 insertions(+), 198 deletions(-) create mode 100644 src/mainboard/intel/Clearwater/failover.lds diff --git a/src/mainboard/intel/Clearwater/Config b/src/mainboard/intel/Clearwater/Config index 8e6f301eee..97ad8f8155 100644 --- a/src/mainboard/intel/Clearwater/Config +++ b/src/mainboard/intel/Clearwater/Config @@ -21,11 +21,11 @@ ldscript cpu/i386/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## -mainboardinit cpu/i386/reset16.inc -ldscript cpu/i386/reset16.lds +mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE +ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE -#mainboardinit mainboard/intel/sv2/reset32.inc -#ldscript mainboard/intel/sv2/reset32.lds +mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE +ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE ## ## Include an id string (For safe flashing) @@ -43,10 +43,10 @@ ldscript arch/i386/lib/id.lds ## Things are delicate and we test to see if we should ## failover to another image. -#mainboardinit northbridge/intel/82860/reset_test.inc -#mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE -#mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE -#ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE +mainboardinit northbridge/intel/82860/reset_test.inc +mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE +mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE +ldscript mainboard/intel/Clearwater/failover.lds USE_FALLBACK_IMAGE ### ### O.k. We aren't just an intermediary anymore! @@ -179,7 +179,7 @@ option HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option tabe table ## -#option HAVE_OPTION_TABLE=1 +option HAVE_OPTION_TABLE=1 ## ## Build code for SMP support @@ -226,7 +226,7 @@ nooption MEMORY_HOLE ## If we aren't a fallback image we must be a normal image ## This is useful for optional includes ## -option USE_FALLBACK_IMAGE=0 +option USE_FALLBACK_IMAGE=1 expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE ### @@ -244,8 +244,8 @@ option _RAMBASE=0x00008000 ## For the trick of using cache as ram ## put the fake ram location at this address -option CACHE_RAM_BASE=0xfff70000 -option CACHE_RAM_SIZE=0x00010000 +#option CACHE_RAM_BASE=0xfff70000 +#option CACHE_RAM_SIZE=0x00010000 ## ## Use a small 8K stack @@ -268,7 +268,7 @@ option PYRO_SERIAL=1 ## ## Only use the option table in a normal image ## -#expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE +expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE ## ## Compute the location and size of where this firmware image @@ -282,14 +282,16 @@ expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE* ## Compute the start location and size size of ## The linuxBIOS bootloader. ## -expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +#expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +expr ZKERNEL_START = 0xfff00000 + expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE ## ## Compute where this copy of linuxBIOS will start in the boot rom ## #expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE -expr _ROMBASE = 0xffff0000 - (USE_FALLBACK_IMAGE*0x10000) +expr _ROMBASE = 0xffff0000 - (USE_NORMAL_IMAGE*0x10000) ## ## Compute a range of ROM that can cached to speed of linuxBIOS, diff --git a/src/mainboard/intel/Clearwater/STATUS b/src/mainboard/intel/Clearwater/STATUS index af79f37578..d059feaf24 100644 --- a/src/mainboard/intel/Clearwater/STATUS +++ b/src/mainboard/intel/Clearwater/STATUS @@ -10,7 +10,7 @@ email: pyro@linuxlabs.com status: unstable explanation: Too new to claim stable (even though it seems good) flash-types: Intel 82802ac8 FWH (8Mbit), 82802ab8 (4Mbit) can be substituted -payload-types: etherboot, memtest86 +payload-types: etherboot, memtest86, pforth (an embedded Forth environment) # e.g. linux, plan 9, wince, etc. OS-types: linux # e.g. "Plan 9 interrupts don't work on this chipset" @@ -19,7 +19,7 @@ console-types: serial # vga is unsupported, unstable, or stable vga: unsupported # Last-known-good follows the internationl date standard: day/month/year -last-known-good: 27/10/2002 +last-known-good: 07/11/2002 Comments: Links: Mainboard-revision: 0 (pre-production sample) 1 (production) diff --git a/src/mainboard/intel/Clearwater/example-fallback.config b/src/mainboard/intel/Clearwater/example-fallback.config index 362c375515..48adb8d128 100644 --- a/src/mainboard/intel/Clearwater/example-fallback.config +++ b/src/mainboard/intel/Clearwater/example-fallback.config @@ -1,104 +1,33 @@ -## This will make a target directory of ./fallback -## This is relative to where the configuration file resides in the filesystem -target ./fallback +# This will make a target directory of ./clearwater1 +# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE +# CONFIG TOOL. Make it absolute if you like +target clearwater1 -mainboard supermicro/p4dc6 +# Intel Clearwater (cw2) mainboard +mainboard intel/Clearwater -## Build a fallback not a normal image. -option USE_FALLBACK_IMAGE=1 - -## Build an image for a 512KB rom -## ./fallback/romimage is just the last 64KB which we reserve for the fallback image. -option ROM_SIZE=524288 -#option ROM_SIZE=1048576 - -## Select the maximum size the linuxBIOS code can compile to. -## Allow linuxBIOS to be up to 48KB in size -option ROM_IMAGE_SIZE=49152 - - -## -### The Serial Console -## -## Hardware flow control is currently ignored. - -## Enable the Serial Console +# Enable Serial Console for debugging +# It will come up at 115200,8n1 option SERIAL_CONSOLE=1 -## Select the serial console baud rate. -option TTYS0_BAUD=115200 -#option TTYS0_BAUD=57600 -#option TTYS0_BAUD=38400 -#option TTYS0_BAUD=19200 -#option TTYS0_BAUD=9600 -#option TTYS0_BAUD=4800 -#option TTYS0_BAUD=2400 -#option TTYS0_BAUD=1200 +# Enable MicroCode update and L2 Cache init for PII and PIII +option UPDATE_MICROCODE=1 +#option CONFIGURE_L2_CACHE=1 -# Select the serial console base port -option TTYS0_BASE=0x3f8 +# Use the internal VGA frame buffer device +#option HAVE_FRAMEBUFFER=1 -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -option TTYS0_LCS=0x3 - - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -option DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -option MAXIMUM_CONSOLE_LOGLEVEL=6 - -## Use the elf bootloader option USE_ELF_BOOT=1 -## Select the boot device option USE_GENERIC_ROM=1 -#option BOOT_FLOPPY=1 -#option USE_SERIAL_FILL_INBUF=1 -#option BOOT_IDE=1 -# Load etherboot with the elf bootloader -# The payload command is relative the build directory -# So .. is the directory this config file resides in -payload ../eepro100.ebi +option STD_FLASH=1 +option USE_FALLBACK_IMAGE = 1 -## -## Cpu Speed -## -option CPU_CLOCK_MULTIPLIER=XEON_X8 -#option CPU_CLOCK_MULTIPLIER=XEON_X9 -#option CPU_CLOCK_MULTIPLIER=XEON_X10 -#option CPU_CLOCK_MULTIPLIER=XEON_X11 -#option CPU_CLOCK_MULTIPLIER=XEON_X12 -#option CPU_CLOCK_MULTIPLIER=XEON_X13 -#option CPU_CLOCK_MULTIPLIER=XEON_X14 -#option CPU_CLOCK_MULTIPLIER=XEON_X15 -#option CPU_CLOCK_MULTIPLIER=XEON_X16 -#option CPU_CLOCK_MULTIPLIER=XEON_X17 -#option CPU_CLOCK_MULTIPLIER=XEON_X18 -#option CPU_CLOCK_MULTIPLIER=XEON_X19 -#option CPU_CLOCK_MULTIPLIER=XEON_X19 -#option CPU_CLOCK_MULTIPLIER=XEON_X20 -#option CPU_CLOCK_MULTIPLIER=XEON_X21 -#option CPU_CLOCK_MULTIPLIER=XEON_X22 -#option CPU_CLOCK_MULTIPLIER=XEON_X23 +option HAVE_PIRQ_TABLE=1 -## -## Select power on after power fail setting -option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON -#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON +option DEFAULT_CONSOLE_LOGLEVEL=8 + +#payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf diff --git a/src/mainboard/intel/Clearwater/example-normal.config b/src/mainboard/intel/Clearwater/example-normal.config index 0ce189d2bf..0ed317b4fb 100644 --- a/src/mainboard/intel/Clearwater/example-normal.config +++ b/src/mainboard/intel/Clearwater/example-normal.config @@ -1,105 +1,43 @@ -## This will make a target directory of ./normal -## This is relative to where the configuration file resides in the filesystem -target ./normal +# This will make a target directory of ./winfast +# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE +# CONFIG TOOL. Make it absolute if you like +target clearwater-primary -mainboard supermicro/p4dc6 +# Leadtek WinFast 6300 MAX mainboard +mainboard intel/Clearwater -## Build a normal not a fallback image. -option USE_FALLBACK_IMAGE=0 - -## Build an image for a 512KB rom -## ./normal/romimage is the entire rom image except for the last 64KB -## which are reserved for the fallback image. -option ROM_SIZE=524288 -#option ROM_SIZE=1048576 - -## Select the maximum size the linuxBIOS code can compile to. -## Allow linuxBIOS to be up to 48KB in size -option ROM_IMAGE_SIZE=49152 - - -## -### The Serial Console -## -## Hardware flow control is currently ignored. - -## Enable the Serial Console +# Enable Serial Console for debugging +# It will come up at 115200,8n1 option SERIAL_CONSOLE=1 -## Select the serial console baud rate. -option TTYS0_BAUD=115200 -#option TTYS0_BAUD=57600 -#option TTYS0_BAUD=38400 -#option TTYS0_BAUD=19200 -#option TTYS0_BAUD=9600 -#option TTYS0_BAUD=4800 -#option TTYS0_BAUD=2400 -#option TTYS0_BAUD=1200 +# Enable MicroCode update and L2 Cache init for PII and PIII +option UPDATE_MICROCODE=1 +#option CONFIGURE_L2_CACHE=1 -# Select the serial console base port -option TTYS0_BASE=0x3f8 +# Use the internal VGA frame buffer device +#option HAVE_FRAMEBUFFER=1 -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -option TTYS0_LCS=0x3 - - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -option DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -option MAXIMUM_CONSOLE_LOGLEVEL=8 - -## Use the elf bootloader option USE_ELF_BOOT=1 -## Select the boot device option USE_GENERIC_ROM=1 -#option BOOT_FLOPPY=1 -#option USE_SERIAL_FILL_INBUF=1 -#option BOOT_IDE=1 -# Load etherboot with the elf bootloader -# The payload command is relative the build directory -# So .. is the directory this config file resides in -payload ../eepro100.ebi +option STD_FLASH=1 +option USE_FALLBACK_IMAGE = 0 -## -## Cpu Speed -## -#option CPU_CLOCK_MULTIPLIER=XEON_X8 -#option CPU_CLOCK_MULTIPLIER=XEON_X9 -#option CPU_CLOCK_MULTIPLIER=XEON_X10 -#option CPU_CLOCK_MULTIPLIER=XEON_X11 -#option CPU_CLOCK_MULTIPLIER=XEON_X12 -#option CPU_CLOCK_MULTIPLIER=XEON_X13 -#option CPU_CLOCK_MULTIPLIER=XEON_X14 -#option CPU_CLOCK_MULTIPLIER=XEON_X15 -#option CPU_CLOCK_MULTIPLIER=XEON_X16 -option CPU_CLOCK_MULTIPLIER=XEON_X17 -#option CPU_CLOCK_MULTIPLIER=XEON_X18 -#option CPU_CLOCK_MULTIPLIER=XEON_X19 -#option CPU_CLOCK_MULTIPLIER=XEON_X19 -#option CPU_CLOCK_MULTIPLIER=XEON_X20 -#option CPU_CLOCK_MULTIPLIER=XEON_X21 -#option CPU_CLOCK_MULTIPLIER=XEON_X22 -#option CPU_CLOCK_MULTIPLIER=XEON_X23 +option HAVE_PIRQ_TABLE=1 -## -## Select power on after power fail setting -option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON -#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON +option DEFAULT_CONSOLE_LOGLEVEL=8 +payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf + +# Path to your kernel (vmlinux) +# NOTE; you need a path to your test12 kernel here. +#linux /usr/src/linux-2.2.17-beoboot-pyro1 +#linux /usr/src/linux-2.4.0-test12 + +# Kernel command line parameters +#commandline root=/dev/nftla1 + +# We're using disk on chip. Tell it where to find the docipl code +#docipl northsouthbridge/sis/630/ipl.S diff --git a/src/mainboard/intel/Clearwater/failover.lds b/src/mainboard/intel/Clearwater/failover.lds new file mode 100644 index 0000000000..309a33adb9 --- /dev/null +++ b/src/mainboard/intel/Clearwater/failover.lds @@ -0,0 +1 @@ + __normal_image = 0xf0000 - 8;