From f323adb19fc43589c8df1c029f64621f90da7084 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 25 Jun 2025 08:48:12 +0800
Subject: [PATCH] soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz
 to 52MHz

Set SPI NOR clock from 26MHz to 52MHz to improve boot time.

BUG=b:379008996
BRANCH=none
TEST=Verified clock rate via oscilloscope, and measure boot time with
cbmem
(previous) Total Time: 800,539
(now) Total Time: 739,292

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe3df8200417fa9a8292bfd3c29339b7d125e3c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/mt8189/pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c
index ffd48987e4..c05c39227c 100644
--- a/src/soc/mediatek/mt8189/pll.c
+++ b/src/soc/mediatek/mt8189/pll.c
@@ -261,7 +261,7 @@ static const struct mux_sel mux_sels[] = {
 	{ .id = CLK_TOP_DP_SEL, .sel = 4 },
 	{ .id = CLK_TOP_EDP_SEL, .sel = 4 },
 	{ .id = CLK_TOP_EDP_FAVT_SEL, .sel = 4 },
-	{ .id = CLK_TOP_SFLASH_SEL, .sel = 0 },
+	{ .id = CLK_TOP_SFLASH_SEL, .sel = 2 },
 	{ .id = CLK_TOP_ECC_SEL, .sel = 5 },
 };